Freescale Semiconductor,inc.

Hillel Miller

Jayanta Bhadra

Mrinal Bose

Amol V Bhinge

George W Wood

Edward L Swarthout

Yaniv Fais

Sharon Goldschlager

Amit Hermony

Prashant U Naphade

Pankaj Sharma

Ekaterina A Trofimova

Robert S Slater

Kenneth G Davis

A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.

Trace reconstruction for silicon validation of asynchronous systems-on-chip

A method, computer program product, and data processing system that controls test packets that are sent to a coordinating computer system is provided. A node computer system runs a test case that results in one or more test result packets. Control data structures are received from one or more coordinating computer systems. The resulting test result packets are compared to the one or more received data structures. The comparison reveals whether one or more of the test result packets include results requested by the coordinating computer systems. Test result packets are selected when the comparison reveals that the selected test result packets include results requested by the coordinating computer systems. Selected test result packets are sent to one of the coordinating computer systems and unselected test result packets are discarded by the node.

Improving test pattern coverage through parallel discard, flow control, and quality metrics

An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Stream based stimulus definition and delivery via interworking

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Austin, TX, United States of America

Hillel Miller