Marvell International Limited

Dreambig Semiconductor Inc.

Optibase Ltd.

Firquest LLC

Other

Cisco Technology, Inc.

Corigine (Hong Kong) Limited

Viewgraphics, Inc.

Hillel Gazit

Gevorg Torjyan

Sohail Syed

Hon Luu

Sohail A Syed

Pranab Ghosh

Kevin Deierling

a content addressable memory circuit is provided that includes a memory array that includes multiple memory devices that include memory locations that share a memory address and are coupled for simultaneous access. Hash logic is operative to use modulo math to determine a memory address based upon non-X values within an IP address key. Memory controller logic is operative to cause a memory device in the memory array to store the received IP address key in a memory location at the determined memory address, in a format that includes a field-size value indicative of a number of non-X values within a received IP address key and that includes non-X values within the received IP address key.

Data compression for LPM in TCAM

A content addressable memory circuit is provided that includes: multiple integrated circuit memory devices that include memory address locations that share common memory addresses; buffer circuits operatively coupled to the memory devices; a hash table that includes a plurality of hash values that each corresponds to one or more key values; one or more processor circuits configured with instructions to perform operations that include: assigning each hash value to a memory address location based upon a first portion of the hash value; storing each key value at a memory address location assigned to a first portion of a hash value that corresponds to the key value; copying a first key value from a first memory address location within a memory device to a buffer circuit operatively coupled to the memory device; copying the first key value from the buffer circuit operatively coupled to the memory device to a second memory address location of the memory device; and assigning a second portion of a hash value that corresponds to the first key value to the second memory address location of the memory device.

Content relocation and hash updates in algorithmic TCAM

A content addressable memory circuit comprising: a memory device array including multiple memory devices coupled for simultaneous access to memory address locations that share a common memory address; multiple virtual modules (VMs), wherein each VM stores a data set that includes key values stored within an assigned memory address range within the memory array that are assigned to the VM; wherein each VM, stores a virtual hash table in non-transitory memory, that associates hash values with memory addresses within an assigned memory address range of the VM; hash logic is operable to determine a hash value, based upon a received key value and a respective assigned memory address range; and memory controller logic is operable to use a virtual hash table to access a memory address in an assigned memory address range, based upon the determined hash value.

Virtual modules in TCAM

A method is provided to control a content addressable memory that includes multiple integrated circuit memory devices that include common memory address locations and that are coupled for simultaneous access to the common memory address locations, the method comprising; determining a hash value, based upon a received key value, that corresponds to a common memory address location of the multiple memory devices; providing activity status information for multiple common memory address locations of the memory devices; selecting a memory devices from which to output stored content data from the corresponding common memory address location, based upon storage activity status information; and causing the selected one or more memory devices to output stored content data.

Algorithmic TCAM with storage activity-based read

A ternary content addressable memory is provided comprising; a memory device that includes a plurality of memory address locations; hash logic operative to determine a hash value, based upon a ternary key, wherein the determined hash value corresponds to a memory address location of the memory device; an encoder operable to convert the ternary key to a binary bit representation; wherein converting includes determining binary mapping bits based upon number and positions of ternary non-X (don't care) value bits of the ternary key; wherein converting further includes determining a different binary data bit to correspond to each different ternary non-X value bit of the ternary key; and memory controller logic to cause the memory device to store the binary bit representation at the memory address location that corresponds to the determined hash value.

Algorithmic TCAM with compressed key encoding

A NOT logic circuit is provided comprising: one or more memory devices; wherein a first memory address location of the one or more memory devices stores first content data, wherein the first content data includes a first ternary value and a corresponding first priority value, wherein the first ternary value includes a continuous sequence of X-state values that represent a first range of non-X ternary values; wherein a second memory address of the one or more memory device stores second content data that includes a second ternary value and a corresponding second priority value, wherein the second ternary value includes a continuous sequence of non-X state values represent a non-X ternary value that is within the first range of non-X ternary values; an interface is coupled to receive a ternary value from a processing device; comparator circuitry operable to compare a received ternary key with the outputted first ternary value and to compare the received ternary key with the outputted second ternary value; priority encoder logic operable to, return the outputted first priority value on a condition that the received ternary key matches the first ternary value and the received ternary key does not match second ternary value, and return the outputted second priority value on a condition that the received ternary key matches the first ternary value and that the received ternary key matches the second ternary value; and detection logic operable to send a return to the processing device on a condition of a return of the first priority value.

TCAM-based not logic

Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM modules, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.

Hybrid memory device for lookup operations

Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM module, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.

Computer circuitry is provided for fast caching, which includes a memory, a processor, and a cache. The memory stores a data block. The processor retrieves the data block from the memory and determines whether to store the data block in the cache. The cache performs a first hash function on the data block in response to the processor determining to store the data block in the cache. The cache performs a second hash function on the data block if the first hash function results in a collision.

Methods and apparatus for performing fast caching

Systems and techniques relating to processing of network communications include, according to an aspect, a network device that includes circuitry configured to receive value bits selected from a group consisting of a zero bit, a one bit, and a don't care bit; and circuitry configured to store encoded representations of the value bits for use in network packet routing, wherein the encoded representations are position bits selected from a group consisting of a zero bit and a one bit; wherein the circuitry configured to store includes a first memory location and a second memory location that each eliminate a different combination of the value bits from being available for storage respectively in the first memory location and the second memory location.

Apparatus and methods to compress data in a network device and perform ternary content addressable memory (TCAM) processing

Multi-port memory circuitry includes single-port memory circuitry, and arbitration logic circuitry that accepts multiple memory queries for the single-port memory circuitry and prevents the multiple memory queries from addressing conflicting portions of the single-port memory circuitry within a single clock cycle. The arbitration logic circuitry may include conflict-resolution logic circuitry that determines whether multiple memory queries address conflicting portions of the single-port memory circuitry. The single-port memory circuitry may be divided into a plurality of sub-arrays, and the conflict-resolution logic circuitry determines whether the multiple memory queries address overlapping groups of sub-arrays. The single-port memory circuitry may be a content-addressable memory or a random-access memory. The multi-port memory circuitry may be part of a shared-memory, multi-processor apparatus. Each memory query may include a profile identifying at least one portion of the single-port memory circuitry targeted by the query, and the conflict-resolution logic circuitry would examine each profile.

Multi-port memory

The present disclosure describes systems and techniques relating to accessing data stored in Ternary Content Addressable Memory (TCAM). According to an aspect of the described systems and techniques, a device includes: several blocks of TCAM (Ternary Content Addressable Memory); a hash RAM (Random Access Memory); and processor electronics configured to pre-process control records to (i) identify a subset of bits of the control records, giving priority to bits with no X value, (ii) load the hash RAM based on the identified subset of the bits to be used for hashing of search records to find locations in the several blocks of TCAM, and (iii) order the control records in the several blocks of TCAM in accordance with the identified subset of the bits.

Reducing power consumption in ternary content addressable memory (TCAM)

The present disclosure describes systems and techniques relating to processing of network communications. According to an aspect of the described systems and techniques, a network device includes a content addressable memory (CAM) device including random access memory (RAM) devices; and a register configured to store a value for the RAM devices of the CAM device; wherein the CAM device is configured to retrieve data stored in the RAM devices of the CAM device, at a received address offset by the value stored in the register, for comparison to at least a portion of a search string received from a network processor to handle network packet processing.

Network device architecture to support algorithmic content addressable memory (CAM) processing

The present disclosure describes systems and techniques relating to calculation of array statistics. According to an aspect of the described systems and techniques, a device includes: a memory configured to store a data array and a counter array, wherein the data array includes multiple values, and each of the multiple values is encoded in a respective row of the data array, and wherein the counter array includes multiple counters, respective columns of the counter array correspond to respective ones of the counters, and rows of the counter array correspond with bit significance positions spanning the multiple counters; and processor electronics configured to add up a number bits found in respective columns of the data array using respective ones of the multiple counters.

Accelerated calculation of array statistics

The present disclosure describes systems and techniques relating to processing of network communications. According to an aspect of the described systems and techniques, a network device includes a random access memory (RAM); a buffer coupled with the RAM; circuitry configured to copy data from a location in the RAM to the buffer responsive to a received identifier corresponding to a search key corresponding to a received packet; and circuitry configured to compare the data copied to the buffer with the search key to provide a result for use in forwarding of the packet, wherein don't care bits for the comparison are determined from a count of don't care bits encoded in a portion of the location in the RAM indicated by the identifier.

Growing community of inventors

Palo Alto, CA, United States of America

Hillel Gazit