U.S. Philips Corporation

Alcatel

Societe Anonyme De Telecommunications

Hikmet Sari

Georges M Karam

Lydie Desperben

Said Moridi

Georges Bonnerot

Marc Moeneclaey

In a transmission method in a multiple access radiocommunication system with orthogonal transmission resources, to cater for a number of users greater than the number of transmission resources of the system, at least one of the transmission resources is shared at a given time by at least two users. The users sharing a transmission resource change with time so as to divide the deterioration of the signal to noise ratio resulting from such sharing as evenly as possible between the various users. The deterioration of the signal to noise ratio is further reduced by differentiating the signals corresponding to users sharing the same resource at a given time in terms of their transmit level.

Transmission method for use in a multiple access radiocommunication system

The invention provides a method of increasing by M, where M is any integer, the number N, where N is any integer greater than or equal to 2, of calls set up between a central unit and remote units of a code division multiple access network, N first group calls plus M second group calls being able to be set up simultaneously in this way and each using an internal spreading code and an external scrambling code. In accordance with the invention, first interference caused by first group calls in each second group call is synthesized and the first synthesized interference caused by first group calls is subtracted from each second group call. Similarly, a first interference caused by second group calls in each first group call is synthesized, and the first synthesized interference caused by second group calls is subtracted from each first group call.

Method of increasing the capacity of a CDMA network, and associated units

Using CDMA encoding and spectrum spreading with a factor N, more than N messages are transmitted although N is a theoretical limit for this type of encoding. Encoding uses orthogonal sequences for a first group of N messages and random or pseudo-random sequences PN for a second group of M-N additional messages. On reception, the N messages of the first group are decoded and detected. Their interference is subtracted from the second group of M-N messages before detecting the M-N messages. In a second iteration, the interference of the M-N messages using PN sequences is estimated and subtracted from the N first messages before a second detection on the first group of N messages. Detection is then repeated for the second group of M-N messages after subtracting the interference of the first group of N messages and the mutual interference of the M-N messages.

CDMA method with increased capacity

A device for reducing the jitter caused by pointer adjustments in a digital telecommunication network comprising of a circuit inserting in the vicinity of each phase step caused by a pointer adjustment, a plurality of smoothing phase steps in accordance with a deterministic smoothing pattern in order to eliminate, after having passed through a conventional desynchronizer, the quantifying effects of the phase steps. Provision also is made, for the case in which each phase step caused by a pointer adjustment comprises a plurality of bits, in that a control circuit is present to resolve the step into a plurality of elementary steps and to control the insertion of these steps in a manner matched to the rate of occurrence of pointer adjustments. In particular, the device applies to networks based on Synchronous Digital Hierarchy.

Device for reducing jitter caused by pointer adjustments in a digital

An adaptive predistortion circuit with memory for a digital transmission system includes a set (10) of input registers storing various consecutive data symbols a predistortion circuit (11) for predistorting the data of the consecutive data symbols before they pass through a modulator (14) and then through an amplifier (15) and an adaptation circuit (19) which, in response to a demodulation (16, 17.sub.1, 17.sub.2, 18.sub.1, 18.sub.2) of the stream of transmitted data symbols continuously adapts the predistortion circuit (11) to the stream of input data symbols. The adaptation circuit (19) includes a set (21) of counters/accumulators which determine the center of gravity of the smeared spots (clouds) created by the distortion by calculating a set of errors that is used for adapting the predistortion circuit (11). Preferably, the predistortion circuit is a random access memory. In order to reduce the size of this random access memory the symmetry of the constellation is used and therefore at data input the constellation is reduced to a quarter of the constellation. Reverse operations are thus necessary at the output and in the adaptation loop.

Adaptive predistortion circuit with memory

An adaptive predistortion circuit for a digital transmission system includes a predistortion circuit (52.sub.1, 52.sub.2, 52.sub.3) for predistorting the input data before they pass through a modulator (56) and then through an amplifier (57), and an adaptation circuit (61.sub.1, 61.sub.2, 61.sub.3) for continuously adapting the predistortion circuit to the stream of input data in response to a demodulation of the stream of transmitted data. The predistortion circuit further includes an encoder (51) which, on a first path, in response to digital data a.sub.k, generates digital data b.sub.k which leave a first predistortion circuit (52.sub.1) in a predistorted manner in-phase with the symbol clock, on a second path, digital data c.sub.k which leave a second distortion circuit (52.sub.2) in a predistorted manner phase-shifted by T/3 relative to the symbol clock and on a third path, digital data d.sub.k which leave a third predistortion circuit (52.sub.3) in a predistorted manner phase-shifted by 2T/3 relative to the symbol clock. The signals b.sub.k, c.sub. k and d.sub.k are obtained by means of a polynomial encoding. The encoding may be performed by shift registers (62.sub.1 . . . 62.sub.I) addressing a memory (63) or, by a transversal filter (71.sub.1, 71.sub.2, 71.sub.3). It may also be obtained by means of an analog transmission filter (81) followed by samplers (81.sub.1, 82.sub.2, 82.sub.3).

Adaptive predistortion circuit for a digital transmission system

Predistortion arrangement (9) for a digital transmission system transmits complex input data of a constellation by means of a modulator (14) and a power amplifier (15) which distorts the data. The arrangement comprising a predistortion circuit (11) which predistorts the input data in opposite sense before they pass through the amplifier and a transmit filter (10) which applies oversampled filtered data encoded with 2N bits to the predistortion circuit (11) at the rate k/T. The predistortion circuit (11) first determines approximate values of the predistorted data on the basis of a portion of 2M bits of the field of 2N bits (M&lt;N), which data are thereafter revised with the aid of the remaining portion of said field. The predistortion circuit includes for each channel a memory (112) addressed by the field of M bits which produces the approximate values of the predistorted data and an interpolation circuit (111) which derives therefrom the revised predistorted data.

Predistortion arrangement for a digital transmission system

An adaptive predistortion circuit for a digital transmission system which comprises a predistortion circuit (52.sub.1, 52.sub.2) predistorting the input data prior to their entering a modulator (56) and thereafter an amplifier (57), and an adaptation circuit (61.sub.1, 61.sub.2) continuously adapting the predistortion circuit to the stream of transmitted data in response to a demodulation of the stream of transmitted data. The predistortion circuit further comprises an encoder (51) which, on the basis of digital data a.sub.k, generates on a first path digital data b.sub.k which leave a first predistortion circuit (52.sub.1) in a predistorted manner and in-phase with the symbol clock, and on a second path digital data c.sub.k which leave a second predistortion circuit (52.sub.2) in a predistorted manner and in phase-opposition to the symbol clock. The signals b.sub.k and c.sub.k are obtained by means of a polynomial encoding. The encoding may be effected with the aid of shift registers (62.sub.1 . . . 62.sub.I) addressing a memory.

Adaptive predistortion circuit

A circuit for recovering the carrier of a digitally modulated wave comprising a voltage-controlled oscillator (17) that is controlled by an error signal .epsilon.(.phi.) in order to adjust the phase of the oscillator, the modulated wave being introduced into two channels, the one in phase (10) and the other in quadrature (20) with the carrier, the two channels being joined together by a phase comparator arrangement (25) which produces the error signal and a sampling clock (H1). The phase comparator arrangement (25) alternately operates as a phase detector and as a frequency detector and therefore comprises an apparatus for selecting received signal points with the aid of selection zones formed by ring segments, situated around certain states of the signal constellation. The signals of the in-phase and quadrature channels are used to address a memory (26) that contains the information belonging to or not belonging to the signal point received in one of the selected zones as well as the amplitude and the error sign that relate thereto. In addition, the phase comparator arrangement (25) comprises apparaturs (28, 29) for generating the sampling clock (H1) which, in the acquisition mode (off-hook), validates the basic clock H only for these selected zones and, in the permanent mode (on-hook), validates all the edges of the clock H for forming the sampling clock.

Circuit for recovering the carrier in digital transmission systems

A circuit for recovering the carrier of a digitally modulated wave having a phase symmetry 2.pi./M, wherein M is the order of the symmetry, includes means for automatic and fast acquisition comprising a voltage-controlled oscillator having an output supplying said carrier and a control input to which an error signal .epsilon.(.phi.) is applied in order to change the oscillator phase and to adjust it to the phase of the digital modulated wave. This wave is introduced in two channels, one being in phase and the other being in quadrature with the carrier, each comprising the series arrangement of: a demodulator, a low-pass filter, reconstruction means for reconstructing a signal and for determining the error between the filtered and reconstructed signals, the quadrature channel comprising in addition a 90.degree. phase shifter, the two channels being joined together with the aid of a phase comparator arrangement which produces a comparison signal and a variable-rate sampling clock. With the representation of the signals from the in-phase and quadrature channels defining the states of a signal constellation of the modulated wave, the phase comparator arrangement comprises means for selecting received signal points with the aid of zones which are centered on or eccentric to certain diagonal states of the signal constellation, and means for generating the sampling clock by eliminating from a recovered symbol clock an active edge capable of validating zero crossings of the comparator signal which do not correspond to a phase difference equal to 2k.pi./M (k and M integers).

Circuit for recovering the carrier wave in digital transmission systems

A digital data receiving arrangement, which adapts itself to channel variations of a transmission system, comprises an adaptive receiver stage (11), having an adaptive equalizer and at least one sampler, and producing, at a certain rate, complex samples y.sub.k from the input signal x(t), a decision circuit (14) supplying detected complex samples a.sub.k and an adaptive timing recovery circuit (12) determining the optimal sampling instant by minimizing a quadratic function J which represents the difference between y.sub.k and a.sub.k. The adaptive timing recovery circuit comprises a device (121) for shaping a primary clock signal in accordance with a secondary clock signal, whose period is twice the period of the primary clock and whose consecutive ascending edges are spaced in time by T.sub.1 and T.sub.2, said secondary clock producing alternately two sampling instants .tau. and .tau.+.DELTA..tau.. By minimizing the function J, on the basis of the difference determined for two instants .tau..sub.k and .tau..sub.k +.DELTA..tau., the control of the timing recovery is defined for the consecutive sampling instants .tau..sub.k and .tau..sub.k+1.

Arrangement for receiving digital data comprising an arrangement for

A method of and an arrangement for determining the optimum position of the reference tap of a master adaptive equalizer which adapts itself to variations of the transmission characteristics of a transmission channel in a digital system for transmitting data which are in general complex, such adaptation being effected by modifying sets of coefficients of transversal filters which modify the transmitted symbols. Simultaneously with the operation of the master adaptive equalizer, and in consecutive analyzing periods, a selection is made in accordance with a selection algorithm of the optimum positions of the reference taps of transversal filters in a slave adaptive equalizer, the coefficients of which are adapted in accordance with an adaptation algorithm. A comparison is made between the symbols supplied by the master and slave adaptive equalizers in accordance with an error criterion, and when the error criterion indicates that the slave adaptive equalizer provides the best results the reference tap position and coefficients thereof are transferred to the master adaptive equalizer.

Method of and arrangement for determining the optimum position of the

An adaptive equalizer arrangement for digital transmission system comprises at the output of the transmission channel a first in-phase path and in parallel with this first path, a second quadrature path, both paths being of the non-recursive transversal filter type having n branches and (n-1) delay circuits between the inputs of these branches, each of these n branches comprising, arranged in series, a mixer, a low-pass filter, a multiplier, and having their outputs connected to an adder which is followed by a sampling circuit and thereafter by a comparator circuit to decide the symbols to be transmitted from the outputs of these paths. The arrangement also comprises a third control path which comprises two subtracting circuits to determine the differences between the signals before and after decision and a control circuit of a voltage-controlled oscillator, 2n phase shifters and 2n multipliers.

Combined adaptive equalization and demodulation circuit

An auto-adaptive amplitude-equalizing arrangement for digital radio links having an intermediate-frequency signal input, a transversal filter and a circuit for the control of the filter. The transversal filter comprises a delay circuit providing, with respect to the intermediate-frequency signal input, a delay T equal to (2k-1)/4F.sub.c, where k is a positive integer and F.sub.c the center frequency of the intermediate-frequency signal, a first and a second multiplication circuit whose inputs are respectively connected to the output of the delay circuit and to the intermediate-frequency signal input, and an adder connected to the outputs of the multiplication circuits. The first multiplication circuit may be an analog amplifier whose gain is controlled by the control circuit, or may comprise a fixed-gain amplifier and a digitally controlled attenuator, the control inputs of the attenuator being connected to the count outputs of an up/down-counter, which is controlled by a zero comparator connected to the output of the control circuit.

Auto-adaptive amplitude-equalizing arrangement for digital radio links

Carrier recovery arrangement in a receiving system for digital data which are transmitted by sixteen-state amplitude and phase modulation (16 QAM), the arrangement having, successively six parallel paths (V.sub.1 -V.sub.6) each including the series arrangement of a multiplying circuit (M.sub.i) and a low-pass filter (F.sub.i); a selection circuit for selecting one of the three pairs of filter output signals thus obtained; a phase control circuit having a Costas signal processing circuit receiving the selected pair of signals and producing a signal representative of the phase error of the received signal, a filter and a voltage-controlled oscillator; and a phase-shifting circuit receiving the output signal of the oscillator in order to couple this output signal to respective second inputs of the multiplying circuits (M.sub.1)-(M.sub.6), this signal coupling being effected with a phase shift zero for (M.sub.1), .theta. for (M.sub.3), 2.theta. for (M.sub.5), and with a phase shift .pi./2 for (M.sub.2), .theta.+.pi./2 for (M.sub.4), and 2.theta.+.pi./2 for (M.sub.6), where .theta. is equal to tan.sup.-1 (1/2).

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