Semiconductor Energy Laboratory Co., Ltd.

Hikaru Tamura

Yoshiyuki Kurokawa

Takayuki Ikeda

Takeshi Aoki

Munehiro Kozuma

Masataka Ikeda

Atsuo Isobe

Wataru Uesugi

Shunpei Yamazaki

Takahiko Ishizu

Takeshi Osada

Naoaki Tsutsui

Toshiki Hamada

Tomoaki Atsumi

Takuro Ohmaru

Takashi Hamada

Jiro Imada

Kazuko Yamawaki

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Semiconductor device and manufacturing method thereof

An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

Electronic device

A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

Logic circuit, processing unit, electronic component, and electronic device

Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuitis used as a memory circuit with a function of performing an arithmetic operation. One of a circuitand a circuithas a region overlapping with at least part of the other of the circuitand the circuit. Accordingly, the circuitcan perform the arithmetic operation that is essentially performed in the circuit; thus, a burden of the arithmetic operation on the circuitcan be reduced. Moreover, the number of times of data transmission and reception between the circuitsandcan be reduced. Furthermore, the circuitfunctioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuitis suppressed.

Semiconductor device and healthcare system

Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuitis used as a memory circuit with a function of performing an arithmetic operation. One of a circuitand a circuithas a region overlapping with at least part of the other of the circuitand the circuitAccordingly, the circuitcan perform the arithmetic operation that is essentially performed in the circuitthus, a burden of the arithmetic operation on the circuitcan be reduced. Moreover, the number of times of data transmission and reception between the circuitsandcan be reduced. Furthermore, the circuitfunctioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuitis suppressed.

Method for operating a semiconductor device having a memory circuit with an OS transistor and an arithmetic circuit

A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.

Semiconductor device, electronic component, and electronic device

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Kanagawa, Japan

Hikaru Tamura