Nec Corporation

Hikaru Hida

Keiichi Ohata

Masaki Ogawa

Muneo Fukaishi

In an N-channel HEMT, a channel layer having an electron affinity .chi..sub.1, a spacer layer having an electron affinity .chi..sub.2, and an electron supply layer having an electron affinity .chi..sub.3 smaller than the electron affinity .chi..sub.1 and larger than the electron affinity .chi..sub.2 are laminated in this sequence. Both the channel layer and the electron supply layer include indium (In), and a percentage composition of indium in the channel layer is larger than a percentage composition of indium in the electron supply layer.

Reliable HEMT with small parasitic resistance

A compound semiconductor memory has a second semiconductor layer (undoped AlGaAs hetero-barrier layer), a third semiconductor layer (n type InGaAs layer), a fourth semiconductor layer (undoped AlGaAs layer) and a gate electrode of WSi selectively deposited in order on an n type first semiconductor layer (n type GaAs channel layer). A drain electrode and a source electrode, which are electrically connected to the first semiconductor layer are formed on those areas of the first semiconductor layer where the second semiconductor layer or the like is not formed. At this time, the potential barrier of a floating gate (third semiconductor layer) on the gate electrode side is set higher than the potential barrier of the floating gate (first semiconductor layer) on the channel layer side.

NAND or NOR compound semiconductor memory

Compound semiconductor memory with floating gate

In an FET structure, an n-type AlGaAs electron supplying layer is provided above a GaAs channel layer, and a low-resistivity n-type GaAs contact layer (the first semiconductor layer) is provided between the source/drain electrode and the electron supplying layer. A high-resistivity AlGaAs layer (the second semiconductor layer) is formed on the sidewalls of the contact layer and the immediately adjacent region between the gate electrode and the contact layer. According to the present invention, since a semiconductor film is used as the thin film formed on the sidewall and the adjacent electron supplying layer instead of a conventional insulating film, and moreover since AlGaAs is substantially lattice matched to GaAs and has a larger band width, parasitic resistance is reduced significantly, and the fluctuation of device performance properties is prevented while still maintaining high breakdown voltage. A semiconductor layer having a conduction type opposite that of the contact layer may also be used in place of the high resistivity AlGaAs layer.

Field effect transistor with recessed gate

A field effect transistor comprises a semiconductor substrate, a first layer made of a semiconductor having an electron affinity and the first layer being formed on the semiconductor substrate, a second layer made of material having electron affinity smaller than that of the first layer formed on the first layer, a length of the second layer being longer than that of the first layer, source and drain regions formed on the semiconductor substrate, the source and drain regions being separated through a lamination of the first and second layer, a gate electrode formed on the second layer, a gate length of the gate electrode being shorter than that of the second layer and being shorter than that of the first layer and the gate electrode being separated from the source and drains region through the second layer.

Field effect transistor

The main surface of a semiconductor substrate, on which a field effect transistor is formed, coincides with the (nm0) lattice plane of the substrate and drain electrode thereof is oriented to flow drain current in a direction parallel to the [mn0] or [mn0] axis, wherein n and m independently represent an arbitrary integer, provided that n and m are not 0 at the same time, and that the quotient n/m (m is not zero) is not an integer. Accordingly, the plane orientation of the substrate and the direction of the drain current have a relationship such that no piezoelectric charges are induced in the channel region of the field effect transistor. Therefore, substantially no piezoelectric charges are generated even when a stress is produced in the dielectric layer formed on the substrate. Moreover, deterioration and variation in the electric characteristics due to the variation in the thickness of the dielectric layer are minimized.

Field effect transistor having a low threshold voltage shift

A semiconductor device comprising a first semiconductor layer, a second semiconductor layer on the first layer, a source electrode and a drain electrode both in contact with the first layer, and a hole or electron injection electrode and a gate electrode both formed on the second layer; wherein the second semiconductor is one that has an electron affinity smaller than the first semiconductor when holes are injected or has a sum of an electron affinity and a band gap greater than the first semiconductor when electrons are injected; and wherein the injection electrode and the gate electrode are placed between the source electrode and the drain electrode in this order. In such device, the current driving capability can easily be increased by controlling the injection amount of holes or electrons and the current modulation can easily be controlled by a small capacitance gate electrode; and so operation at an extra-high frequency and an extra-high speed becomes possible.

High speed semiconductor device and an optelectronic device

The semiconductor device of the present invention includes on one and the same substrate a first transistor having a first semiconductor layer with high-impurity density on which is provided a second semiconductor layer with low-impurity density, where the first semiconductor layer being of N type and having electron affinity greater than that of the second semiconductor layer, and is equipped with a control electrode provided on the second semiconductor layer and at least two ohmic electrodes that are electrically connected to the first semiconductor layer on both sides of the control electrode, and a second transistor having a third semiconductor layer with low-impurity density provided on top of the second semiconductor layer on the first semiconductor layer, and is equipped with a control electrode provided on the third semiconductor layer and at least two ohmic electrodes that are electrically connected to the first semiconductor layer on both sides of the control electrode. Further, by setting the first semiconductor layer to be a P-type semiconductor having the sum of the electron affinity and the energy gap smaller than the sum of the electron affinity and the energy gap of the second semiconductor layer, there can be obtained a semiconductor using holes as carriers.

Semiconductor device having compound semiconductor FET of E/D structure

An atomic planar-doped field-effect transistor is disclosed, which is featured by a channel region of a limited thickness between source and drain with at least one atomic planar-doped layer formed therein and a barrier layer or layers provided on the upper or lower side or on the both sides of the channel region. The channel region is formed of a semiconductor of a low impurity concentration or of an n-type with the atomic planar-doped layer having high concentration donor impurities or of a p-type with the atomic planar-doped layer having high concentration acceptor impurities. The upper barrier layer is provided between the channel region and a gate electrode and the lower barrier layer, if present, is provided between the channel region and a substrate. They are formed of a semiconductor of a low impurity concentration which is different from the semiconductor of the channel region and makes a heterojunction with the channel region and which has a smaller electron affinity than the semiconductor of the channel region having the donor planar-doped layer or a larger value of a sum of electron affinity and energy gap than the semiconductor of the channel region having the acceptor planar-doped layer. With the upper barrier layer, the transistor of the present invention has a large gate-forward turn-on voltage. The short channel effects are suppressed by adding the lower barrier layer to the transistor.

Atomic planar-doped field-effect transistor

A high speed and high power transistor includes a first layer of a first semiconductor material, a second layer of a second semiconductor material formed on the first layer, the second semiconductor material having a smaller electron affinity than the first semiconductor material, first and second electrode positioned ends of the second layer, respectively, in contact with the first layer, and a control electrode formed on the second layer between the first and second electrodes, the control electrode injecting holes into the second layer in accordance with an input signal to induce an electron channel between the first and second electrodes.

High speed and power transistor

For high speed operation and improvement in transconductance, there is disclosed a heterojunction field-effect device comprising, a first layer of a first compound semiconductor material having a relatively high donor impurity concentration, a second layer of a second compound semiconductor material formed on the first layer and having a relatively low donor impurity concentration and a relatively large electron affinity, a third layer of high-purity compound semiconductor material formed on the second layer and having a relatively small electron affinity, a gate electrode formed on the third layer, a source electrode formed on one side of the gate electrode and electrically connected to the first and second layers, and a drain electrode formed on the other side of the gate electrode and electrically connected to the first and second layers, so that a carrier-accumulation layer takes place in the second layer of the relatively low donor impurity concentration due to the difference in electron affinity between the second and third layers.

Heterojunction field-effect device

A semiconductor device including a first semiconductor layer having a low carrier density, a second semiconductor layer on the first semiconductor layer and having a low carrier density, a third semiconductor layer on the second semiconductor layer, a fourth semiconductor layer on the third semiconductor layer and effective to inject holes into the second semiconductor layer through the third semiconductor layer for inducing a channel of, for example, electrons in the second semiconductor layer in proximity to and along the interface between the second and third semiconductor layers, and a pair of ohmic contact regions extending through the second and third semiconductor layers for providing ohmic contact with the second semiconductor layer for permitting modulation of the conductance between the ohmic contact regions when holes, for example, are injected from the fourth semiconductor layer into the second semiconductor layer. The device has double heterojunctions, one between the first and second semiconductor layers and the other between the second and third semiconductor layers, thus providing FET mode and bipolar mode of operation.

Growing community of inventors

Tokyo, Japan

Hikaru Hida