Samsung Electronics Co., Ltd.

Hijung Kim

Seongjin Cho

Jungmin You

Seong-Jin Cho

Hoyoun Kim

Kwangchol Choe

Jung Min You

Jaepil Lee

Kwangsook Noh

A memory device includes a memory cell array including a plurality of memory cells coupled to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation based on a weighted access count on the memory cell array, a register configured to store a weighted access count for each of a plurality of row addresses; an accumulator configured to accumulate a current weighted access count corresponding to an access spacing to the weighted access count stored in the register, and a calculator configured to calculate the access spacing.

Memory device, memory system including the same and method of operating the same

A memory device includes a memory cell array including a plurality of rows, an ECC engine configured to determine a health level for each of the plurality of rows based on the number of corrections of errors of data read from each of the plurality of rows, a control logic configured to determine a victim row address based on the health level and the number of accesses for each of the plurality of rows, and a refresh control circuit configured to perform a refresh on a row corresponding to the determined victim row address.

Memory device and operating method with mechanism to determine victim rows for refreshing

A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

Memory device, memory system having the same, and method of operating the same

A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

Memory device, memory system having the same and operating method thereof

Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.

Growing community of inventors

Suwon-si, South Korea

Hijung Kim