Silicon Storage Technology, Inc.

Information Storage Devices, Inc.

University of California

Winbond Electronics Corporation

Agency for Science, Technology and Research

Hieu Van Tran

Nhan Do

Anh Ly

Thuan Vu

Vipin Tiwari

Hung Quoc Nguyen

Stanley Hong

Mark Reiten

Steven Lemke

Sang Thanh Nguyen

Stephen Trinh

Vishal Sarin

Loc Bao Hoang

Sakhawat M Khan

William Saiki

Hien Pham

Farnood Merrikh Bayat

Dmitri Strukov

Xinjie Guo

Xian Liu

Kha Nguyen

Jack Frayer

Nasrin Jaffari

Jeng-Wei Yang

Chien-Sheng Su

George J Korsh

Han Tran

Feng Zhou

James Brennan, Jr

Isao Nojima

Sheng-Hsiung Hsueh

Steve Choi

Wingfu AAron Lau

Dana Lee

Trevor A Blyth

Bomy A Chen

Man-Tang Wu

Anthony Dunne

Michael S Briner

Chun-Ming Chen

Nha Nguyen

Amitay Levi

Samar K Saha

Parviz Ghazavi

Sukyoon Yoon

Henry A Om'Mani

Hung O Nguyen

Peter Holzmann

Zhixian Chen

Santosh Hariharan

Viet Tan Nguyen

Nghia Le

Toan Le

Louisa Schneider

Hsuan Liang

Phil Klotzkin

Chunming Wang

Ya-Fen Lin

Jinho Kim

Xiaozhou Qian

Prateep Tuntasood

Kai Man Yue

Richard T Simko

Chun-Mai Liu

Catherine Decobert

Yuri Tkachev

Mandana Tadayoni

Albert V Kordesch

Qing Rao

Pavel Klinger

Xinpeng Wang

Hung Thanh Nguyen

Ning Bai

Kung-Yen Su

Elbert Lin

Tam Huu Tran

Shiuh-Luen Wang

Ryan Mei

Claire Zhu

Boyce W Jarrett

Fan Luo

Susmita Karmakar

Niang Hangzo

Nataraj S Bindiganavale

Geoff Jackson

Duc Nguyen

Wang Xinpeng

Henry Tran

Guo-Qiang Lo

Man Tang Wu

Lihsin Chang

Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2, n≤2, and p≤2.

Row decoder and row address scheme in a memory system

Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.

Split array architecture for analog neural memory in a deep learning artificial neural network

A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

Neural network classifier using array of three-gate non-volatile memory cells

Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

Output array neuron conversion and calibration for analog neural memory in deep learning artificial neural network

A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.

Memory device of non-volatile memory cells

Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.

Analog neural memory array in artificial neural network with source line pulldown mechanism

An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

Deep learning neural network classifier using non-volatile memory array

A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, fourth lines each electrically connect the drain regions in one of the memory cell columns, and a plurality of transistors each electrically connected in series with one of the fourth lines. The synapses receive a first plurality of inputs as electrical voltages on gates of the transistors, and provide a first plurality of outputs as electrical currents on the third lines.

In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Input and output blocks for an array of memory cells

A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

Neural network device

Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

Multiple row programming operation in artificial neural network array

Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

Read and programming decoding system for analog neural memory

Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed. In some embodiments, a method is performed to determine in real-time a bias value to apply to one or more memory cells in a neural network. In other embodiments, a bias voltage is determined from a lookup table and is applied to a terminal of a memory cell during a read operation.

Determination of a bias voltage to apply to one or more memory cells in a neural network

Numerous examples are disclosed of an improved grouping and error correction system for non-volatile memory cells. In one example, a system comprises a memory array comprising non-volatile memory cells arranged into rows and columns, wherein a non-volatile memory cell of the memory array stores a first bit of a first data grouping and a second bit of a second data grouping, and wherein the first grouping is backed by a first ECC block and the second grouping is backed by a second ECC block.

Grouping and error correction for non-volatile memory cells

Growing community of inventors

San Jose, CA, United States of America

Hieu Van Tran