Thomson Components-Mostek Corporation

Texas Instruments Corporation

Mostek Corporation

Hiep Van Tran

A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resistive circuitry which allow bootstrapped voltages.

Darlington bicmos driver circuit

A high-speed level shifter converts ECL logic levels to CMOS logic levels for use in an ECL BiCMOS circuit. A CMOS inverter (34) is connected to the output of an emitter coupled pair through a resistor (36). A current reference circuit ensures that the voltage drop across the resistor (36) is such to shift the ECL logic level to the trip point of the CMOS buffer.

ECL-to-CMOS level conversion for use in ECL-BiCMOS circuit

A multiple input differential sense amplifier including a pair of signal inputs and comprising a bank of n-channel MOS transistors for receiving said multiple inputs for connection to one of said signal inputs. The other of said signal inputs can be provided with a fixed bias input, or a complementary input from a complementary bank of n-channel MOS transistors.

Multiple-input sense amplifier with two CMOS differential stages driving

A high speed CMOS NOR gate employs a pair of cross-coupled inverters and a dual set of N-channel pulldown transistors (202, 203) at each of the nodes between the two inverters, together with small pullup transistor (205) on the output terminal that is permanently energized and a switchable large pullup transistor (220) that is a link between the second inverter output and the first inverter input.

High speed NOR gate

CMOS memory arrangement including a circuit for setting the dataline voltage at a predetermined bias level, the circuit comprising four MOS transistors, the first, second and third and the first and fourth thereof being connected in respective series from VCC to ground, the gates of the first and second transistors being connected to ground, the bias level being established between the second and third transistors with the gate of the third transistor being connected to the node therebetween.

CMOS memory arrangement

A synchronizing buffer arrangement for a CMOS memory with output drive transistors receiving one of a pair of input data signals, and being subject to the pull-up and pull-down support of the other of said data signals.

CMOS output buffer

A common mode gain enhancing CMOS differential sense amplifier for a static RAM memory, straddled by level shifting circuits during the respective differential inputs to the sense amplifier.

CMOS sense amplifier with level shifter

A circuit adapted for use in comparing voltages in a manner that is insensitive to power supply variations includes a pair of reference cells controlling the reference voltage of a sense amplifier through control of a pair of reference transistors and an input circuit for conditioning data having a matched input pair of transistors, so that input data will control the voltage on the input terminal of a sense amplifier in a manner such that both inputs to the sense amp track voltage, thermal and processing variations.

Power supply dependent voltage reference circuit

A differential sense amplifier employs a central region having two current paths each having a P- and N-type transistor in series, all four transistors having a common gate connection. Each input transistor has its source connected to the top of one current path and its drain connected to the bottom of the other current path, to apply the maximum differential input.

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Carrollton, TX, United States of America

Hiep Van Tran