Texas Instruments Corporation

Other

Thomson Components-mostek Corporation

Hiep V Tran

David Barry Scott

Richard X Gu

Luan A Dang

Alan Gatherer

Hugh Pryor McAdams

Shunichi Sukegawa

Shivaling S Mahant-Shetti

Hugh Thomas Mair

Uming U Ko

Sanjive Agarwala

Claude E Tew

Joseph H Neal

James L Conner

Wei Dong

Kevin L Kornher

Pak Kuen Fung

Ngai Hung Hong

Systems design and methods are provided for maintaining the memory array stability while reducing power consumption in the form of leakage current in a memory array. One embodiment discloses a memory array system, which comprises a plurality of memory cells, a monitor cell array, a controller, and voltage regulator circuits. The controller receives information from the monitor cell array, determines the state of stability, and adjusts the voltage regulators accordingly to ensure the memory array stability and minimizes leakage.

Low leakage high stability memory array system

A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the precharge node to charge the precharge node and the second switch is responsive to the one of a high or low voltage at the precharge node to control the first switch charging the precharge node. The first switch is preferably a p-channel transistor and the second switch is preferably an n-channel transistor. The circuit also includes an output terminal, an inverter coupled between the precharge node and the output terminal and feedback circuitry coupled between the output terminal and coupled to the second switch to provide the charge state of the precharge node to the second switch. The circuit further includes a pair of transistors having serially connected current paths, the serially connected current paths being coupled between the precharge node and a reference source.

Self-selecting precharged domino logic circuit

System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement) with a plurality of switches (such as switch) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

Potential and rate adjust header switch circuitry reducing transient current

Systems and methods are provided for reducing leakage current and maintaining high performance in a static random access memory (SRAM). One embodiment discloses a memory array system operative to store data bits in individually addressable rows and columns. The memory array system comprises a plurality of memory blocks, each of the plurality of memory blocks having a plurality of memory rows and a row peripheral circuit operative to switch a memory block from a retention mode to an activation mode in response to an addressing of a memory row within the memory block.

High performance, low-leakage static random access memory (SRAM)

A method of operating a memory circuit having a plurality of blocks of memory cells (-) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells () is selected in response to a first address signal (RA). A row of memory cells (-) in the first block of memory cells is selected in response to a second address signal (RA). A first voltage is applied to a first power supply terminal () of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal () of another block of memory cells () of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

Virtual ground circuit for reducing SRAM standby power

An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical grouping of memory cells, configured to bias a subset of the set based on a memory address associated therewith. In another embodiment, a method includes receiving a memory address associated with the hierarchical grouping of memory cells and biasing a subset of the hierarchical grouping of memory cells based on the memory address.

High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode

A method of operating a memory circuit having a plurality of blocks of memory cells () is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells () is selected in response to a first address signal (RA). A row of memory cells () in the first block of memory cells is selected in response to a second address signal (RA). A first voltage is applied to a first power supply terminal () of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal () of another block of memory cells () of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

Systems and methods are provided for reducing power consumption in the form of leakage current in a memory array. One embodiment discloses a memory array system. The memory array system comprises a plurality of memory cells and a programmable switching control circuit. The programmable switching control circuit is operative to arrange the plurality of memory cells in a standard configuration in an activation mode and to arrange the plurality of memory cells in a stacked configuration in a retention mode.

Programmable stackable memory array system

In an equalizer filter unit, the filter is divided into a plurality of sequential segments. While all the components of the equalizer unit multiply data signal groups by the a coefficient signal group, in only one segment are the coefficient signal groups updated. The data and the coefficient signal groups are periodically transferred to the next sequential filter segment while the filter segments are reconfigured in the original sequential order. In this manner, the each data signal group interacts with a coefficient signal group in the original sequential order. Because the coefficients are updated in only one of the filter segments, the amount of apparatus required for processing signal groups is reduced.

Apparatus and method for a reduced component equalizer circuit

A charge pump circuit. The circuit includes an input node for receiving a clock signal having cycles. The charge pump circuit includes a pump circuit coupled to the input node, including a first capacitor and having an output node coupled to a second capacitor, the pump circuit operating to provide a predetermined charge the second capacitor in response to a cycle of the clock signal. The predetermined charge corresponds to the amount of charge accumulated on the first capacitor during the cycle of the clock signal.

Charge mirror circuit

In a transceiver unit including an adaptive equalizer filter unit, apparatus is provided for reducing or compressing the number of bits representing an error signal. The apparatus replaces a plurality of the most significant logic signal bits with a single bits while transferring the sign logic signal bit and the logic signal bits of lesser significance unchanged. Because of the reduction in the number of logic signal bits, the number of components implementing the multiplier unit in the adaptive filter unit can be reduced (i.e., in each stage of the adaptive filter). The reduction of the apparatus implementing the processing the error signal results in the same equilibrium value of the error signal, however, the time to reach this equilibrium value is increased.

Apparatus and method for an error signal compression technique in a fast adaptive equalizer circuit

A circuit for improving the performance of a charging capacitor inverter used in VCO and similar circuits. The disclosed approach is used to provide both trip point and charging current delay control to reduce the amount of &ldquo;jitter&rdquo; associated with the circuit. Trip point delay control is accomplished by adding an in-line transistor, output in a typical charged capacitor inverter, between the charging capacitor and the circuit. The threshold of this transistor is controlled by a dc bias level (control voltage) which allows this transistor to turn &ldquo;ON&rdquo; or &ldquo;OFF&rdquo; when the node voltage of the capacitor reaches the controllable preset level. Further control of the circuit's delay is obtained by means of circuitry which allows the amount of capacitor charging current to be selected.

Jitter reduction circuit

A data converter ( ) comprising an input (I &prime;-I &prime;) for receiving a digital word and an output (V ) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL &prime;-BL &prime;) formed with an alignment in a first dimension and a plurality of word lines (WL &prime;-WL &prime;) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string ( &prime;) comprising a plurality of series connected resistive elements (R &prime;-R &prime;). The string comprises a plurality of voltage taps (T &prime;-T &prime;), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST &prime;-ST &prime;) coupled between the plurality of voltage taps and the output. Lastly, for each of a majority of the plurality of word lines the word line is coupled to at least one gate of a switching transistor located on a first side of the word line and to at least one gate of a switching transistor located on a second side of the word line, wherein the second side is opposite the first side.

Data converter with vertical resistor meander

In a fast adaptive filter unit, an update unit replaces the multiplier unit which generates a product of the filter constant, the error signal and data signal and adding this product to a previously generated coefficient with a reduced complexity unit. The reduced complexity unit determines the sign of the product and whether the product is zero or non-zero. As a result of this determination a two bit signal is generated which is used to either increment or decrement the count in a register in the counter unit. The count held by the register is the coefficient signal, the coefficient signal being updated by each additional operation. In order to prevent the register from over-flowing, a second counter applies a signal periodically to the counter unit which decrements the magnitude of coefficient signal stored in the register by one count.

Apparatus and method for a reduced complexity tap leakage unit in a fast adaptive filter circuit

A stacked cache memory system and method is provided. The stacked cache memory system (10) may include a memory cell array (22) coupled to a cache system (30). The memory cell array (22) stores and retrieves a data signal. Recently retrieved data signals are stored in a number of sense-amp memory cells (52) within the cache system (30). A column select system (32) is coupled to the cache system (30). A logic subsystem (12) controls the column select system (32) such that the column select system (32) directs the data signal from the memory cell array (22) to a sense-amp system (34) or directs a stored data output signal from the cache system (30) to a switching system (36). The sense-amp system (34) senses and amplifies the data signal and produces an amplified data output signal. The switching system (36) is coupled to the sense-amp system (34) and the cache system (30) and operates to select between the amplified data output signal from the sense-amp system (34) and the stored data output signal from the cache system (30).

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Carrollton, TX, United States of America

Hiep V Tran