Samsung Electronics Co., Ltd.

Avago Technologies General IP (Singapore) Pte. Ltd.

Altera Corporation

Silicon Bridge Inc.

Agere Systems Inc.

Hiep The Pham

Chih-Wei Yao

Adam Benjamin Healey

Chaitanya Palusa

Volodymyr Shvydun

Xiong Liu

Zhiqiang Huang

Tomasz Prokop

Mei Luo

Nader Sharifi

Minsoo Choi

Hyojun Kim

A wireline transceiver system includes a predriver configured to generate a signal; a source-series termination (SST) driver configured to receive the generated signal; and a replica driver configured to continuously generate bias voltages in real time to modulate current of a push-pull current source of the SST driver based on a voltage of the received signal across a process, voltage, and temperature (PVT) range.

Hybrid source-series termination driver with constant output swing

A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

Serdes with pin sharing

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

DC-coupled SERDES receiver

An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.

System and method for providing fast-settling quadrature detection and correction

A synchronized I/Q detection circuit is provided. A first subset of input signals and, subsequently, a second subset of input signals are provided by a first multiplexer and received by a first phase detector. Outputs of the first phase detector are receiving, by a first reset and sampling circuit. A second set of input signals are provided by a second multiplexer and received by a second phase detector, from a second multiplexer, while the first multiplexer receives the first and second subsets of input signals. The first subset of input signals has a same phase order as the second set of input signals, and the second subset of input signals has a different phase order than the second set of input signals. Outputs of the second phase detector are received by a second reset and sampling circuit. A comparator outputs a detected phase difference based on the outputs of the first and second reset and sampling circuits.

Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit

A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.

Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the communication channel, ranging from ultra short reach applications to very short reach, medium reach, long reach and extra long reach applications.

Modular low power serializer-deserializer

Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

Baud rate phase detector with no error latches

A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on the first set of estimated data bits and at least one pre-cursor coefficient.

Method and apparatus for pre-cursor intersymbol interference correction

An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.

Pipelined decision feedback equalization in an interleaved serializer/deserializer receiver

A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.

Code forwarding and clock generation for transmitter repeaters

Various embodiments of a hybrid class AB super follower circuit are provided. One embodiment is a follower circuit comprising: an input node for receiving an input voltage signal; an output node for driving a capacitive load based on the input voltage signal; a transistor Mhaving a gate terminal connected to the input node for receiving the input voltage signal, a source terminal connected to the output node, and a drain terminal; a feedback loop comprising a second transistor M, a third transistor Mand a fourth transistor M, wherein: the gate and source terminals of the second transistor Mare connected to a current source I, and the drain terminal of the second transistor Mis connected to the output node; the source terminal of the third transistor Mis connected to the current source Iand the drain terminal of the third transistor Mis connected to a current source I; the gate terminal of the fourth transistor Mis connected to the drain terminal of the third transistor M, the drain terminal of the fourth transistor Mis connected to the output node, and the source terminal of the fourth transistor Mis connected to a ground; and a replica bias circuit for providing a voltage bias signal to the gate terminal of the third transistor.

Growing community of inventors

Campbell, CA, United States of America

Hiep The Pham