United Test and Assembly Center Limited

St Assembly Test Services Inc.

United Test and Assembly Test Center Ltd.

Utac Headquarters Pte. Ltd.

Utac - United Test and Assembly Test Center Ltd.

Hien Boon Tan

Anthony Yi Sheng Sun

Danny Retuta

Susanto Tanary

Mary Annie Cheong

Chuen Khiang Wang

Byung Joon Han

Jae Hak Yee

Zheng Zheng

Rahamat Bidin

Soon Huat James Tan

Jeffrey David Punzalan

Ravi Kanth Kolan

Krishnamoorthi Sivalingam

Hua Hong Tan

Roel Adeva Robles

Hao Liu

Yi Sheng Anthony Sun

Francis YongWee Poh

Richard Te Gan

Nirmal K Sharma

Rodel Manalac

Gaurav Mehta

Seong Kwang Brandon Kim

Roland Cordero

Jefferey D Punzalan

Beng Kuan Lim

Kolan Ravi Kanth

Anthony Sun-Yi Sheng

Patrick Low Tse Hoong

Clifton Teik Lyk Law

Sin Nee Song

Steven Yu Feng Yao

Henry Iksan

Francis Koon Seong Poh

Jaime Siat

A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

Method of producing a semiconductor package

A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. Then, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.

An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

High density chip scale leadframe package and method of manufacturing the package

This invention includes a heat sink structure for use in a semiconductor package that includes a ring structure with down sets and a heat sink connected to the ring structure. The down sets can be slanted or V-shaped. The invention also includes a method of manufacturing a semiconductor package that includes inserting a substrate with an attached semiconductor chip in a first mold portion, placing a heat sink structure on top of a portion of the substrate, placing a mold release film onto a second mold portion, clamping a second mold portion onto a portion of the heat sink structure, injecting an encapsulant into a mold cavity, wherein the encapsulant surrounds portions of the substrate, semiconductor chip and heat sink structure, curing the encapsulant, whereby the heat sink structure adheres to the encapsulant and singulating the encapsulated assembly to form a semiconductor package.

Thermally enhanced semiconductor package and method of producing the same

A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.

Semiconductor package with under bump metallization aligned with open vias

A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free from encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

Structurally-enhanced integrated circuit package and method of manufacture

A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.

Multi-die IC package and manufacturing method

A stacked die semiconductor package that includes a substrate with a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions. The package also includes a first semiconductor chip having a non-active surface in contact with the adhesive portions, and an active surface being electrically connected to the substrate. In the package, a second semiconductor chip the non-active surface of the second semiconductor chip is attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween. The active surface of the second semiconductor chip is electrically connected to the substrate. An encapsulant material covers the first and second semiconductor chips and their associated electrical connections. The encapsulating material fills the at least one gap between the plurality of adhesive portions and thereby encapsulates the second semiconductor chip and its associated electrical connection.

Stacked die packages

A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

Semiconductor chip package and method of manufacture

A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.

Leadframe enhancement and method of producing a multi-row semiconductor package

A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates a support which securely holds the chip in place with adhesive for assembly.

Cavity chip package

An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.

High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing package

An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.

Integrated circuit package with leadframe enhancement and method of manufacturing the same

Growing community of inventors

Singapore, Singapore

Hien Boon Tan