National Semiconductor Corporation

Hiekyung Chun-Min

Chih-Sieh Teng

Tian-I Liou

An N+ poly-to-N+ silicon capacitor structure is provided by adding a single mask step to a standard CMOS process flow. The capacitor oxide between the N+ poly plate and the N+ silicon plate is grown simultaneously with gate oxide for the MOSFET devices. A high dose, deep phosphorous implant is employed to form the N+ substrate plate. This results in an excellent capacitance voltage coefficient. The resulting thin interplate oxide leads to high capacitance per unit area and, thus, small die size.

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Los Altos, CA, United States of America

Hiekyung Chun-Min