Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Longitude Semiconductor S.a.r.l.

Longitude Licensing Limited

Ultramemory Inc.

Hideyuki Yoko

Hiroki Fujisawa

Ryuji Takishita

Chikara Kondo

Kayoko Shibata

Naohisa Nishioka

Ryuuji Takishita

Masayuki M Nakamura

Akira Ide

Naoki Ogawa

Kentaro Hara

Yasuyuki Shigezane

Akihiko Takizawa

Yuji Motoyama

Kenichi Tanamachi

Kazuo Hidaka

Masatoshi Hasegawa

Shigeru Nakahara

A semiconductor device according to an embodiment of the present invention which can rapidly output data while being relatively low cost includes: a plurality of memory each including: a strobe signal transmission path having, in this order, a strobe input terminal, a strobe delay circuit, and a strobe output terminal; a plurality of data output circuits connected to a downstream side of the strobe delay circuit of the strobe signal transmission path; and a data output bus connected to the plurality of data output circuits; and a controller including: a strobe circuit which inputs the strobe signal to the strobe input terminal; a data buffer circuit which temporarily stores the data outputted from the data output terminal; and a delay adjustment circuit which adjusts a delay amount of the strobe delay circuit so as to decrease a difference between the memory in delay of the strobe signal outputted from the strobe output terminal relative to the strobe signal outputted from the strobe circuit.

Semiconductor memory devices and controller including adjustable strobe delay

A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.

Semiconductor device chip selection

A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.

Semiconductor device and timing control method for the same

Semiconductor device and information processing system having the same

A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.

Semiconductor memory device, method of adjusting the same and information processing system including the same

To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

Semiconductor device semiconductor device testing method, and data processing system

A semiconductor device according to the present invention includes plural core chips CCto CCto which mutually different pieces of chip identification information LID are allocated, and an interface chip IF that controls the core chips CCto CC. The interface chip IF receives address information ADD for specifying a memory cell, and supplies in common a part of the address information to the core chips CCto CCas chip selection information SEL to be compared with the chip identification information LID. With this configuration, it appears from a controller that an address space is simply enlarged. Therefore, an interface that is same as that for a conventional semiconductor memory device can be used.

Semiconductor device and information processing system including the same

Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.

Semiconductor memory device and information processing system including the same

A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

Semiconductor system

To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.

Semiconductor device, semiconductor device testing method, and data processing system

A semiconductor device includes a first semiconductor chip that includes a driver circuit, a second semiconductor chip that includes a receiver circuit and an external terminal, and a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to any one of the through silicon vias and the external terminal, the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and the input switching circuit activates any one of the tri-state inverters.

Semiconductor device

A semiconductor device according to the present invention includes plural controlled chips CCto CCthat hold mutually different layer information, and a control chip IF that supplies in common layer address signals Ato Aand a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals Ato Ais transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals Ato Areach the controlled chips earlier than the command signal ICMD.

A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

Growing community of inventors

Tokyo, Japan

Hideyuki Yoko