Hitachi, Ltd.

Mitsubishi Denki Kabushiki Kaisha

Japan Atomic Energy Research Institute

Hideyuki Yagi

Masaharu Moriyasu

Megumi Ohmine

Katsuyuki Ara

Toshitsugu Ohmura

Moriaki Fuyama

Masanobu Hanazono

Yutaka Misawa

Masahiro Okamura

Keiichi Kuniya

Yasumichi Yasuda

Shuroku Sakurada

Tadaaki Kariya

Osamu Asai

Hideo Ikeda

Keiichi Morita

Yoichi Nakashima

Masayoshi Sugiyama

Masao Tsuruoka

Isao Kojima

Masao Iimura

Hideo Imeda

Junichiro Horiuchi

A method of manufacturing a heat resisting magnetic scale is disclosed which comprises a manufacturing process in which at least a part of a heat resisting base is heated and immediately cooled for the purpose of fusing the heated part to the base and changing both the magnetic characteristics of the part of the base which has been heated and the Curie point of the part which has been heated is raised to 100.degree. C. or higher.

Method of manufacturing heat resisting magnetic scale

A method of manufacturing a heat resisting magnetic scale is disclosed which comprises a manufacturing process in which at least a part of a heat resisting base is heated and a manufacturing process in which the part which has been heated is immediately cooled down for the purpose of changing the magnetic characteristics of the part of the base which has been heated and the Curie point of the part which has been heated is raised to 100.degree. C. or higher. A heating resisting magnetic scale which cannot be demagnetized at high temperatures and cannot be separated even if it is subjected to rapid change in temperatures, and which exhibits excellent stability and measuring precision.

An improved dielectric insulator separated substrate for semiconductor integrated circuits is obtained by forming a lamination of at least three thin-polycrystalline layers and dielectric films interposed therebetween on a thick polycrystalline layer of the substrate. A thickness x(.mu.m) of each of the thin-polycrystalline layers is represented by the formula:

Process for producing a dielectric insulator separated substrate

This invention concerns a so-called double-moat uni-surface type semiconductor device in which two concentric moats are provided in one main surface of the substrate and the edges of the two pn-junctions for blocking main circuit voltages applied to the device are exposed in the surfaces of the moats. Semiconductor layers having high impurity concentrations and serving as channel stoppers are formed on the semiconductor layers exposed in the one main surface of the substrate, contiguous to the moats and spaced apart from the pn-junctions, each high impurity concentration layer having the same conductivity type as the semiconductor layer on which it is formed. The moats are filled with surface passivating material.

Semiconductor device with double moat and double channel stoppers

A composite joint system is disclosed in which a composite structure containing carbon fibers embedded in a copper matrix in any configuration, e.g. in one direction, in random directions, in mesh form, spirally or radially is joined to another structure through a brazing material such as solder, Al brazer or Ag brazer. A film of metal such as Ni, Cr, Mo, W, Ta, Ti, Zr, V, an alloy of one or some of such metals, or the combination of some thereof is interposed between the composite structure and the brazing material. The metal film has a good wettability to both the composite structure material and the brazing material.

Composite joint system including composite structure of carbon fibers

In a high-withstand-voltage (high-breakdown voltage) semiconductor device in which the main PN junction is of planar structure and a field limiting ring region is provided outside and around the exposed end of the main PN junction, a groove is formed between the main region to form the main PN junction and the field limiting ring region, the bottom of which groove is shallower than that of each of the regions and in the surface of which groove the end of the main PN junction and one of the ends of the PN junction between the field limiting ring region and the substrate are exposed, and the other end of the PN junction between the field limiting ring region and the substrate is exposed in the surface of another groove whose bottom is deeper than that of the field limiting ring region.

High withstand voltage semiconductor device with shallow grooves between

By forming a metallic coating on a sufficiently cleaned semiconductor substrate through ion plating, a low power loss and high switching speed semiconductor device is obtained which differs from an ordinary semiconductor device with a diffused junction. In an interface between the metallic coating and the semiconductor substrate, a considerably thin metal-injected layer is formed toward the semiconductor substrate. Schottky barrier devices may be formed by the method of the invention.

Method of manufacturing low power loss semiconductor device

Growing community of inventors

Ibaraki, Japan

Hideyuki Yagi