Fujitsu Corporation

Hideyuki Unno

Masaki Ukai

Ryuji Kan

Kenichi Kitamura

Naoya Ishimura

Naozumi Aoki

Matthew Depetro

A mark adding unit adds first information that is erroneously generated error detecting data of first data stored in a first storage area of a memory to the first data and adds second information that is erroneously generated error detecting information of second data stored in a second storage area to the second data. A mark removing unit removes the second information in the second data by rewriting the second information with the error detecting information of the second data without rewriting the first information in the first data when the second storage area out of the first storage area and the second storage area is configured to be usable. An error detecting unit performs an error detecting process of read-out data using information that is added to the read-out data in a case where the data stored in the memory is read out.

Information processing apparatus, and method of controlling information processing apparatus

An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.

Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit

An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.

A transmitting side device () and a receiving side device () are connected to each other via a bus () comprising TAG bits (), data bits () and error detection/correction ECC bits (). The transmitting side device () uses a redundant bit inversion circuit () to invert different bits of the ECC bits () corresponding to trigger signals (&). In the receiving side device (), a determination circuit (), which has received an error report signal () from an error detection/correction circuit (), determines, from the position of an error bit in the ECC bits (), which one of the trigger signals (&) has been transmitted from the transmitting side device ().

Control method of information processing device and information processing device

A data buffer control unit obtains data from a cache according to a command retained in a command queue retaining a command(s) for reading data from the cache, and a magic ID generation circuit generates a magic ID. The data buffer control unit assigns the data obtained from the cache with the magic ID, writes the assigned data to a data buffer, and returns the magic ID to the command queue. When the data buffer control unit receives a read request and the magic ID which is returned to the command queue, it reads the data, which corresponds to the read request, from the command queue and compares the magic ID assigned in the read data and the received magic ID. If the two magic IDs compared by the data buffer control unit are not identical, a packet generator detects an error and reports the error to a host.

Error detection device

When selecting one command within a processor from a plurality of command queues vested with order of priority, the order of priority assigned to the plurality of command queues is dynamically changed so as to select a command, on a priority basis, from a command queue vested with a higher priority from among the plurality of command queues in accordance with the post-change order of priority.

Command selection method and its apparatus

A plurality of system controllerseach comprising a memory mediumand an I/O deviceunder the control of the system controllerare connected to a CPU nodeby way of a plurality of system buses. The CPU nodeexecutes a memory interleave for distributing memory accesses to the system buses(i.e., the system controllers). In performing an I/O access to the I/O device, the CPU nodefirstly inquires from a representative system controller(SC) as to which system bus(i.e., a system controller) has a target I/O deviceand then executes an actual I/O access to the system busreturned in a response from the SC. Even when the CPU nodeexecutes a memory interleave in the case of a memory-mapped I/O, the CPU nodeis not required to manage the location information of the I/O device

Central processing apparatus, control method therefor and information processing system

A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.

Growing community of inventors

Kawasaki, Japan

Hideyuki Unno