Sharp Kabushiki Kaisha Corporation

Sharp Kabushiki Kaishi

Hideyuki Tsuji

Toshiyuki Shinozaki

Toshiaki Kinosada

Toshiaki Miyajima

Masahiro Shiota

Minoru Yoshioka

Mitsuo Matsunami

A heterojunction bipolar transistor having a ballast resistance layer between an AlGaAs emitter layer and an emitter electrode, wherein the ballast resistance layer comprises n-Al Ga As, wherein 0<X<1, and a GaAs selective etching layer is provided between the emitter layer and the ballast resistance layer.

Heterojunction bipolar transistor and its manufacturing process

In the case where ohmic electrodes are formed on a semiconductor wafer, first of all, an insulating layer is formed on the semiconductor wafer, then a resist layer is formed on the insulating layer. Next, apertures for forming electrodes are formed in first regions of the resist layer corresponding to regions where the electrodes are formed, while dummy apertures are also formed in a second region of the resist layer in a rest part other than the first regions. Thereafter, the insulating layer is etched using the resist layer as a mask. With the resist layer remaining, electrode material is accumulated on the surface of the semiconductor wafer, and thereafter, the resist layer is removed. As a result, electrodes with desirable ohmic characteristics are stably formed.

Method of forming ohmic electrodes on semiconductor wafer

vertical power MOSFET which comprises a semiconductive substrate of a first conductivity type serving as drain, an impurity region of a second conductivity type on a part of the surface of the semiconductive substrate, an impurity region of a first conductivity type formed on a part of the surface of the second conductivity type impurity region and serving as source, and a surface portion of a second conductivity type semiconductive substrate between source and drain serving as a channel portion with a gate electrode thereon through an insulating film, so that voltage is applied to the gate electrode to control channel current between source and drain, wherein the first conductivity type semiconductive substrate comprises a low resistivity layer and a high resistivity layer epitaxially formed on the low resistivity layer, and at an interface between the low resistivity layer and the high resistivity layer is provided a convexed portion which projects at least to the high resistivity layer side.

Vertical power MOSFET

Growing community of inventors

Nara, Japan

Hideyuki Tsuji