Fujitsu Corporation

Hideyuki Sakamaki

Hidekazu Osano

Hiroshi Nakayama

Masanori Higeta

Yoshikazu Iwami

Kazuya Takaku

A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Memory controller and information processing apparatus

In a processing system including a processing apparatus, an input/output apparatus and communication apparatuses, the communication apparatus includes: a first instructing unit that issues a configuration change instruction in accordance with set configuration information to the processing apparatus and the input/output apparatus; and a first setting unit that, when an operation change completion notification corresponding to the configuration change instruction is received, sets the configuration information in accordance with a state established after a configuration change, and each of the processing apparatus and the input/output apparatus includes: a second setting unit that sets the configuration information in accordance with the configuration change instruction received from the communication apparatus; a second instructing unit that issues an operation change instruction in accordance with the set configuration information; and a notifying unit that, when the operation change is completed, issues an operation change completion notification to the communication apparatus.

Processing system, communication apparatus, and processing apparatus

A debug system scans a scan memory element group having a plurality of scan memory elements which are connected in series in a semiconductor integrated circuit device and collects data in the scan memory element group. The semiconductor integrated circuit device has an end code register which is provided between an input terminal and an input side of the scan memory element group and holds an end code, a start code register which is provided between an output terminal and an output side of the scan memory element group and holds a start code, and a scan control circuit which controls shift operations of the scan memory element group, the end code register and the start code register, and outputs scan data to the output terminal.

Semiconductor integrated circuit device, method of controlling the semiconductor integrated circuit device and information processing system

A control circuit for receiving data transmitted by a data transmitting circuit and transmitting the received data to a data receiving circuit includes: a data receiving unit for receiving the data transmitted by the data transmitting circuit; a packet analyzing unit for judging whether the data received from the data transmitting circuit is a packet including history acquisition information and reading the history acquisition information from the received data; a history acquisition executing unit for starting or stopping acquiring the history information of the transmission and reception of the data according to the history acquisition information read by the packet analyzing unit to store the history information acquired; and a data transmitting unit for transmitting the packet including the history acquisition information or a packet other than the packet including the history acquisition information to the data receiving circuit.

Control circuit, information processing device, and method of controlling information processing device

According to an aspect of the embodiment, a driver outputs a driver current to a reception LSI, and a receiver included in the reception LSI receives an analog voltage signal corresponding to a value of the driver current as a receiver input. An A/D converter converts the voltage signal of the receiver input to a digital value, and transmits the digital value to a driver current controller in a transmission LSI. The driver current controller adjusts a number of PMOS driving stages in the driver or a number of NMOS driving stages in the driver, to make the digital value of the voltage signal of the receiver input belong to a predetermined range.teh

Method and apparatus for adjusting driver output current and electronic apparatus

A circuit synchronizes parallel data of different timing for transfer. The synchronous data transfer circuit includes a plurality of first flip-flop circuits in which the parallel data are set by a data strobe signal, a plurality of delay circuits, and a plurality of second flip-flop circuits. By configuring the second flip-flop circuits to share generation of a delay amount, the second flip-flop circuits are utilized for data synchronization by the synchronous data transfer circuit. Thus, it becomes possible to configure the delay circuits with a remarkably reduced amount of delay elements.

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Yokohama, Japan

Hideyuki Sakamaki