Mitsubishi Electric Corporation

Tcl Communication Technology Holdings Limited

Hideyuki Nakamizo

Kenichi Tajima

Nobuhiko Ando

Morishige Hieda

Kenji Kawakami

Hiroyuki Mizutani

Mitsuru Mochizuki

Miho Maeda

Yoshinori Takahashi

Kazunori Takahashi

Hiroshi Otsuka

Yukihiro Homma

Keiko Tada

Yusuke Kitsukawa

Hideki Morishige

Osamu Wada

Hifumi Noto

Tatsuya Itoh

Ao Yamashita

Hiroto Sakaki

A signal processing device includes: an amplitude reducing unit to reduce, when a phase shift control signal indicating a phase shift of a transmission wave whose frequency is modulated is output, among amplitudes of a beat signal having a difference frequency between the transmission wave and a reception wave, an amplitude of the beat signal at a timing at which a phase of the transmission wave is shifted in accordance with the phase shift control signal; and a signal converting unit to convert the beat signal whose amplitude at the timing at which the phase of the transmission wave is shifted is reduced by the amplitude reducing unit into a signal in a frequency domain.

Signal processing device and radar device

In a wireless power transmitting device, a control circuit outputs a control signal for setting a frequency and a phase of an F-PLL signal generated by an F-PLL, the F-PLL generates the F-PLL signal having the frequency and the phase set by the control signal output from the control circuit, and a frequency conversion circuit generates a transmission signal by converting a frequency of the F-PLL signal generated by the F-PLL.

Wireless power transmitting device

A local oscillation device according to the present invention includes: a first local oscillator to output a first local oscillation wave synchronized with a reference signal, the first local oscillator being turned on/off on the basis of a control signal; a second local oscillator to output a second local oscillation wave synchronized with the reference signal and the same in frequency and phase as the first local oscillation wave, the second local oscillator being turned on/off on the basis of the control signal; and a path switching circuit coupled to the first local oscillator and the second local oscillator, the path switching circuit switching paths of the first local oscillation wave and the second local oscillation wave on the basis of the control signal or a signal synchronized with the control signal.

Local oscillation device and array antenna device

Included are a first signal exchanger for exchanging a TXI signal and a TXQ signal output from a transmission baseband unit to signal paths and a TX control unit for controlling generation of the TXI signal and the TXQ signal in the transmission baseband unit on the basis of a measurement result of a reception baseband unit before and after exchange of the signals by the first signal exchanger. As a result, a transceiver only needs to have a single local signal generating unit mounted thereon as a local signal generating unit that is an analog circuit.

Transceiver

Synthesizers () for synthesizing feedback signals output from a plurality of antenna modules () are provided. A distortion compensation signal output unit () derives, from a difference between a feedback signal synthesized by the synthesizers () and a base band signal output from a modulation unit (), a distortion compensation coefficient that provides, to the base band signal, distortion characteristics opposite to distortion characteristics of a signal radiated from the phased array antenna and outputs a predistortion signal representing the distortion compensation coefficient to a PD unit ().

Phased array antenna device

A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.

Pulse shift circuit and frequency synthesizer

A mobile communications system including a mobile terminaland a base stationwhich relays communications between a network and the mobile terminal, in which the base stationcan deliver information to the mobile terminalby using an MBMS, in which the base stationsets a flag indicating presence or absence of emergency information to a control channel used for the MBMS, and notifies the presence or absence of the emergency information to the mobile terminalby using the description of the flag set to the control channel for the MBMS.

Mobile communications system, base station, and mobile terminal for distributing emergency messages

Disclosed is a frequency synthesizer including first and second shift register circuitsandeach for outputting PLL setting data on a rising edge of a load enable signal, first and second fractional modulatorsandeach for generating dividing number control data on the basis of the PLL setting data in synchronization with a reference signal, and first and second fractional PLL synthesizersandeach for generating a high frequency signal according to the PLL setting data, the reference signal, and the dividing number control data. By controlling the timing of the load enable signal, the frequency synthesizer carries out phase control between the high frequency signals generated by the first and second fractional PLL synthesizersand

Frequency synthesizer

A signal source synchronization circuit includes: a first TDC circuit that measures a first path delay time which is a time difference between an input time of a trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal; and a second TDC circuit that measures a second path delay time which is a time difference between an input time of the trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal, wherein a first phase shifter adjustment circuit sets a phase adjustment amount corresponding to the first path delay time in a first phase shifter, and a second phase shifter adjustment circuit sets a phase adjustment amount corresponding to the second path delay time in a second phase shifter.

Growing community of inventors

Tokyo, Japan

Hideyuki Nakamizo