Microsoft Technology Licensing, LLC

Hideyuki Nagase

Steve Pronovost

Anuj Bharat Gosalia

Marcus J Andrews

Steven E Lees

Katherine Blair Huffman

Bryan L Langley

Jocelyn Berrendonner

Kiran Muthabatulla

Katie Anderson

Lukasz Konrad Brodzinski

Marcus John Andrews

Described are examples for adjusting display level properties across multiple displays. One or more ranges of display brightness capability values that are supported by a given display device can be received for multiple display devices. For each of the multiple display devices, at least a portion of display brightness capability values in the one or more ranges of display brightness capability values can be mapped to selectable brightness levels available in an operating system. One of the selectable brightness levels can be determined as selected via the operating system. For each of the multiple display devices, a corresponding display brightness capability value mapped to the one of the selectable brightness levels can be determined and indicated to each of the multiple display devices, such that the multiple display devices may set different display brightness capability value brightness, but the brightness may be perceptually similar across the display devices.

Techniques for supporting brightness adjustment across multiple displays

Systems and methods for scheduling coprocessing resources in a computing system are provided without redesigning the coprocessor. In various embodiments, a system of preemptive multitasking is provided achieving benefits over cooperative multitasking by any one or more of (1) executing rendering commands sent to the coprocessor in a different order than they were submitted by applications; (2) preempting the coprocessor during scheduling of non-interruptible hardware; (3) allowing user mode drivers to build work items using command buffers in a way that does not compromise security; (4) preparing DMA buffers for execution while the coprocessor is busy executing a previously prepared DMA buffer; (5) resuming interrupted DMA buffers; and (6) reducing the amount of memory needed to run translated DMA buffers.

Systems and methods for scheduling coprocessor resources in a computing system

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Redmond, WA, United States of America

Hideyuki Nagase