Hitachi, Ltd.

Hideyuki Miyazawa

Yutaka Kobayashi

Jun Murata

Akihiro Tamba

Seigou Yukutake

Hiroyuki Miyazawa

Kyoichiro Asayama

Tomoyuki Someya

A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region. A high impurity conductivity type buried third semiconductor region underlies the said second semiconductor region, and is formed by the same layer as a region isolating the bipolar transistors. This third region is disposed at the bottom surface of said first semiconductor region. A fourth semiconductor region of the second conductivity type is also formed in said first semiconductor region by the same layer used for collector contact regions of the bipolar transistors, and is connected with another end portion of said second semiconductor region, in contact with the third semiconductor region. The fourth semiconductor region is coupled to the input stage circuit, and the third and fourth semiconductor regions form a second PN junction diode.

Semiconductor integrated circuit device including a dielectric breakdown

A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.

Semiconductor integrated circuit device

A method of fabricating semiconductor integrated circuit devices in which a wiring is connected, via a silicon film, to a semiconductor region which is the source region or the drain region of a MISFET. The method comprises a step for introducing impurities for forming a semiconductor region of the MISFET to shallowly form the semiconductor region, a step for forming a silicon film on the main surface of the semiconductor substrate in the region where the impurities are introduced, and a step for diffusing impurities into the semiconductor substrate and for diffusing impurities into a silicon film by the heat treatment so that the silicon film is permitted to possess electric conductivity.

Method of fabricating semiconductor integrated circuit devices including

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Ohme, Japan

Hideyuki Miyazawa