Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Renesas Electronics Corporation

Other

Nec Corporation

Tokyo Shibaura Denki Kabushiki Kaisha

Nec Electronics Corporation

Elpida Memory, Inc.

Hitachi Displays, Ltd.

Hideyuki Matsuoka

Takeshi Sakata

Norikatsu Takaura

Motoyasu Terao

Kiyoo Itoh

Riichiro Takemura

Tomonori Sekiguchi

Satoru Hanzawa

Toshiaki Yamanaka

Shinichiro Kimura

Kenzo Kurotsuchi

Masahiro Moniwa

Tomio Iwasaki

Akio Nishida

Satoru Yamada

Katsuro Watanabe

Kenchi Ito

Naoki Yamamoto

Ryo Nagai

Tsuyoshi Yamauchi

Kenichi Osada

Nozomu Matsuzaki

Kousuke Okuyama

Yuichi Matsui

Kazuo Nakazato

Kota Funayama

Hiroshi Kujirai

Tsuyoshi Tabata

Isamu Asano

Yoshitaka Sasago

Hiroshi Moriya

Eiji Takeda

Shin'ichiro Kimura

Toshiyuki Yoshimura

Osamu Tonomura

Satoru Haga

Teruo Kisu, Legal Representative

Haruko Kisu, Legal Representative

Shuji Ikeda

Shoji Shukuri

Digh Hisamoto

Toshiyuki Mine

Kenichi Kuroda

Masataka Minami

Takeo Shiba

Hiraku Chakihara

Yoshinobu Kimura

Natsuki Yokoyama

Hiromasa Noda

Jun Hayakawa

Eiichi Murakami

Naohiko Irie

Yasuko Yoshida

Akio Shima

Kazunori Tsujimoto

Masaharu Kinoshita

Kazuyoshi Torii

Mitsuharu Tai

Shiro Kamohara

Koichi Inoue

Hisao Asakura

Yasuo Igura

Tsuyoshi Kachi

Shin' Ichiro Kimura

Hajime Tai

Yuji Yoshida

Toshiharu Murayama

Akira Fujimoto

Teruo Kisu

Haruko Kisu

Shin&prime;ichiro Kimura

Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

Semiconductor memory

With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

Semiconductor integrated circuit device

In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

Non-volatile memory device and method of manufacturing the same

A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145&#xb0; C. or higher. The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40 at % or more and 65 at % or less in Zn-Ge-Te.

Memory device

A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

Semiconductor device with ion movement control

The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Storage device

A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If a read access occurs to that address before the next write cycle, data is read out from the register without reading the data from the memory cell array. Without elongating the cycle time, it is possible not only to use a long time to write data into a memory cell therein but also to make longer the interval between the time when a write operation is done and the time when the subsequent read operation is made from that memory cell. As a result, data can be written reliably.

Semiconductor device

A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change recording film contains at least two of Ge, Sb and Te as main constituting elements thereof. The first electrode comprises material of group of Ti, Si and N, or group of Ta, Si and N as main constituting material thereof.

Phase change memory and phase change recording medium

In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

Semiconductor memory cell and method of forming same

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Nishitokyo, Japan

Hideyuki Matsuoka