Fujitsu Corporation

Hideyuki Koinuma

Toshikazu Ueki

Kenichi Mori

Go Sugizaki

Seishi Okada

Masahiro Ichimi

Keiji Miyauchi

Hiroyuki Izui

Hideyuki Kizawa

A hardware thread causes a SleepID register of a WAKEUP signal generation unit to store a SleepID that identifies the hardware thread when suspending a process due to waiting for a process by another CPU. The WAKEUP signal generation unit causes the WAKEUP data register of the WAKEUP signal generation unit to store a SleepID notified by a node when a process that the hardware thread waits ends. The WAKEUP signal generation unit outputs a WAKEUP signal that cancels the stop of the hardware thread to the hardware thread when the SleepIDs of the SleepID register and the WAKEUP data register agree with each other.

Controlling the state of a process between a running and a stopped state by comparing identification information sent prior to execution

An abnormality detection unit provided in at least one node among a plurality of nodes included in an information processing apparatus detects abnormality in a data transmission path of data transmission using a shared memory area sharable in a single node and other node, which is included in the storage unit provided in the single node or other nodes. An error information generation unit provided in the single node generates error information, based on the abnormality detected by the abnormality detection unit, and generates an interrupt with respect to a processor within a self node. The processor provided in the single node performs recovery processing, based on the error information according to the interrupt.

Information processing apparatus, computer-readable recording medium, and control method

An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.

Information processing apparatus, arithmetic device, and information transferring method

At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes.

Information processing apparatus, control method, and computer-readable recording medium

An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Information processing apparatus and access control method

By including detecting an abnormality in a first system common unit; reading a priority indication, from the storage portion, indicating whether or not the first system common unit is to be degenerated when an abnormality occurs in the first system common unit for each of the partitioned portions; carrying out, when an abnormality is detected in a partitioned portion to which the priority indication is set, suspend processing on the information processing apparatus by the system control portion on the partitioned portion; and carrying out degeneration processing for suspending operation of the first system common unit and switching to the second system common unit, quick recovery is achieved when a significant partition is down due to a fault experienced in a common unit.

Degeneration method and information processing apparatus

A LAN terminal equipment comprises a plurality of slots, each capable of accommodating a LAN control board, at least one ROM socket capable of holding a MAC ROM, and an input/output control unit. The input/output control unit determines a correspondence between the LAN control board and the MAC ROM, thereby ensuring the uniqueness of MAC address and also making a primary/spare dual configuration possible.

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Yokohama, Japan

Hideyuki Koinuma