Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Hideyuki Kinoshita

Koji Hashimoto

Eiji Ito

Tetsuya Kamigaki

Kei Watanabe

Toshiyuki Sasaki

Hiroaki Tsunoda

Keisuke Kikutani

Hisataka Meguro

Jun Nishimura

Soichi Yamazaki

Kosuke Horibe

Tomo Hasegawa

Hisashi Harada

A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

Semiconductor device

A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Semiconductor device having dummy bit lines wider than bit lines

NAND flash memory having bit line with smaller width than width of peripheral interconnect line

Method of manufacturing semiconductor device

A method for manufacturing a semiconductor device has forming a first insulating film on a semiconductor substrate, forming an electrode layer on said first insulating film, etching said electrode layer, said first insulating film and said semiconductor substrate of a first predetermined region to form a trench, burying an element-isolating insulating film in said trench, forming a second insulating film on said element-isolating insulating film and above said electrode layer, etching said second insulating film, said electrode layer and said element-isolating insulating film of a second predetermined region to form a gate pattern and a dummy pattern, forming a third insulating film for covering said gate pattern and said dummy pattern, and planarizing said third insulating film using said second insulating film as a stopper.

Semiconductor device, method for manufacturing semiconductor device, and method for manufacturing semiconductor memory device

A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a first line pattern and a first connecting portion in the third member, the first line pattern having a plurality of parallel linear patterns and the first connecting portion connecting the linear patterns on at least one end side of the linear patterns of the first line pattern; etching the second member with the third member as a mask to form a second line pattern and a second connecting portion in the second member, the second line pattern being the same pattern as the first line pattern and the second connecting portion being the same pattern as the first connecting portion; removing the second connecting portion of the second member; and etching the first member with the second member as a mask.

Manufacturing method of semiconductor device and semiconductor device

A NAND-type non-volatile semiconductor memory device has a semiconductor substrate, an element isolation insulating film which is formed on a surface of the semiconductor substrate spaced apart at a predetermined distance from each other, a first insulating film which is formed between the element isolation insulating films on the semiconductor substrate, a floating gate which is formed on the first insulating films, a second insulating gate which is formed on an end region of the floating gate, a control gate which is formed on the second insulating film, and a contact plug which is formed on a surface of the floating gate so that one end of the contact plug is electrically connected to the control gate.

NAND-type non-volatile semiconductor memory device and method of manufacturing the same

A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and removing the connecting portion.

A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.

Semiconductor device with wirings having varying lengths

A NAND nonvolatile semiconductor memory device that has a memory cell array region and a selection gate region, has a semiconductor layer; a gate insulating film disposed on said semiconductor layer; a plurality of first electrode layers selectively disposed on said gate insulating film; a first device isolation insulating film formed in said memory cell array region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; a second device isolation insulating film formed in said selection gate region and extends from between said adjacent first electrode layers into said semiconductor layer for device isolation; an interpoly insulating film formed at least on the top of said first electrode layers and said first device isolation insulating film in said memory cell array region; a second electrode layer disposed on said interpoly insulating film; and a third electrode layer disposed on said second electrode layer, said second device isolation insulating film and the first electrode layers in said selection gate region, wherein the height of the top surface of said second device isolation insulating film is greater than the height of the top surface of said first device isolation insulating film.

NAND nonvolatile semiconductor memory device and method of manufacturing NAND nonvolatile semiconductor memory device

A method of manufacturing a semiconductor device, comprises forming a first mask pattern on an under-layer region, forming a plurality of dummy-line patterns on the under-layer region, the dummy-line patterns being arranged at a first pitch, forming second mask patterns having mask parts provided on long sides of the dummy-line patterns, removing the dummy-line patterns, and etching the under-layer region by using the first mask pattern and the mask parts as a mask.

Method of manufacturing a semiconductor device

A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and etching a region between the linear patterns and the connecting portion to separate the linear patterns and the connecting portion.

A semiconductor memory device, having at least one floating gate, includes a semiconductor substrate; at least one device-isolation region buried in the semiconductor substrate, having a top surface protruding from a top surface of the semiconductor substrate, the top surface of the device isolation region having a concave section that has a depression thereon; at least one gate-insulating film formed on the semiconductor substrate; a first gate formed on the gate-insulating film, the device-isolation region and the depression; a gate-to-gate insulating film formed on the first gate and in the concave section and the depression of the device-isolation region; and a second gate formed on the gate-to-gate insulation film, the depression being filled with the second gate.

Semiconductor device having floating gate and method of producing the same

A semiconductor device comprising, a semiconductor substrate, a first gate insulator film formed on the semiconductor substrate, a floating gate formed on the first gate insulator film, a second insulator film formed on the floating gate, a control gate formed on the second insulator film, and a silicon film doped with nitrogen and an impurity, and interposed between the floating gate and the second gate insulator film and/or between the second gate insulator film and the control gate.

Growing community of inventors

Yokohama, Japan

Hideyuki Kinoshita