Matsushita Electric Industrial Co., Ltd.

Hideyuki Kabuo

Ryutaro Yamanaka

Hidetoshi Suzuki

Minoru Okamoto

Kevin Mark Stone

Hiroyuki Yasoshima

Takashi Taniguchi

Hisakazu Edamatsu

Kazufumi Tanoue

A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.

Communications digital signal processor and digital signal processing method

A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register&#x2014;register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.

Processing unit and processing method

A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.

A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM and PM of an old state is added to each branch metric BM and BM separately. A path metric of a new state N is formed by comparing the value of PM &plus;BM to the value of PM &plus;BM . A path metric of a new state N&plus;2 is formed by comparing the value of PM &plus;BM to PM &plus;BM

A plurality of units identified by respective addresses are disposed in a register file. Each of the units has a data register for storing data representative of a result of an arithmetic operation, a register for storing an overflow flag indicating the presence or absence of an occurrence of overflow in the arithmetic operation, and a register for storing a sign flag providing an indication of which one of a positive and a negative saturation value should replace the arithmetic operation result in the presence of an occurrence of overflow in the arithmetic operation. Each of the flags is updated in response to a write signal concerning its corresponding register. If at the moment when a data register is fed a read signal, a corresponding overflow flag is set, then either a positive or a negative saturation value, whichever corresponds to the sign flag, is generated on the input side of an arithmetic unit.

Data processing system and register file

Two path metrics (PM,, PM,) are read from path metric storing means,, and two path metrics (BM,, BM,) are read from branch metric storing means,. An ACS operation is executed using PM,&plus;MB,and PM,&plus;BM,by comparing means,, adding means,, comparison result storing means,, and selecting means,. In parallel with the ACS operation, an ACS operation is executed using PM,&plus;MB,and PM,&plus;BM,by comparing means,, adding means,, comparison result storing means,, and selecting means

Processor and processing method

In addition to a register file having four general-purpose registers each for storing data, an arithmetic and logic unit for executing an addition instruction, a subtraction instruction, or the like, and a multiplier unit for executing a multiplication instruction, there are provided a controller and a substitute register for storing only data representing the result of operation performed by the multiplier unit in place of any of the four general-purpose registers in the register file. The controller controls the writing and reading of data in and from the register file and the writing and reading of data in and from the substitute register based on a multiplication tag indicative of the one of the four general-purpose registers in place of which the substitute register stores the data representing the result of multiplication and on a multiplication execute flag indicative of whether the data stored in the substitute register is effective or ineffective.

Substitute register for use in a high speed data processor

In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most significant bit, the circuit scale for digit place aligning means is reduced and a double-precision multiplication with an excellent efficiency is realized. Products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device. A digit place alignment addition operation is performed on the obtained products to produce a double-precision multiplication result. In this case, at least two digits are set before the decimal point, thereby allowing each of the products of the high-order word/low-order word of the double-precision multiplicand and the high-order word/low-order word of the double-precision multiplier, to be obtained at a bit width which is larger by at least one bit than a bit width of double precision.

Computing apparatus for double-precision multiplication

In a processor employing a delayed branch method, delayed branch control which does not complicate instruction execution sequence and improves the readability of a program on the assembler level is implemented without providing a control bit in an instruction code. The delayed branch control according to the present invention involves the use of a branch-information storing circuit for storing the occurrence or nonoccurrence of a branch in a specified one of a continuous sequence of cycles immediately before a current execute cycle which are equal in number to delay slots in the processor. In executing a delayed branch instruction, when the branch-information storing circuit stores the occurrence of a branch in the specified cycle, a branch is disabled. This prevents instruction execution sequence from being complicated even when individual branch conditions for consecutive delayed branch instructions are satisfied, so that the program on the assembler level is improved in readability. The branch-information storing circuit can simply be composed of a combination of a shift register, a counter, and a latch.

Method and circuit for delayed branch control and method and circuit for

An arithmetic processor employs two modes of nonpipeline operation and pipeline operation, and is provided with a redundant binary multiplication part for generating redundant binary multiplied results and a supplementary term, first to third intermediate latches for storing two pairs of partial product added results and the supplementary term, a redundant binary accumulation part for accumulating the results of first to third intermediate latches and a value of an accumulation result latch to store the thus accumulated result into the accumulation result latch, and a redundant binary/binary conversion part for converting into a binary numeral the result of the redundant binary multiplication part or the result of the redundant binary accumulation part. Thereby high-speed operations of multiplication instruction and product-sum operation instruction are achieved.

Arithmetic processor and arithmetic method

A data processing device includes first and second blocks which have different processing times and which operate in synchronism with a clock signal. One of the first and second blocks is selected and enabled in accordance with an instruction representing which of the first and second blocks should be selected and enabled. A clock change signal is generated on the basis of the instruction. A period of the clock signal is changed in accordance with the clock change signal.

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Kyoto, Japan

Hideyuki Kabuo