Nec Corporation

Hideyuki Hirata

Hatsuho Murata

Kazuhiko Harasaki

A switching apparatus incorporated in a time division multiplying system has a read control memory for storing addresses indicative of parts of different messages to be transferred to different channels, and a read controller checks the read control memory so as to determine the memory areas of a message memory for selectively transferring the parts of different messages to the channels, thereby making the memory structure simple.

SWITCHING APPARATUS OF TIME DIVISION MULTIPLEXING SYSTEM FOR CONTROLLING DATA TRANSMISSION THROUGH MESSAGE MEMORY SHARED BETWEEN PLURAL CHANNELS, METHOD FOR DATA TRANSMISSION AND INFORMATION STORAGE MEDIUM FOR THE METHOD

An external signal synchronized message signaling apparatus which outputs a particular message to channels of a time division output frame in accordance with a state of an external signal is disclosed. The message signaling apparatus includes a switch buffer, a selector, a message memory, a read control memory and a read controller. Addresses common to the switch buffer and the message memory are stored in the read control memory, and the read controller reads out one of the addresses from the read control memory, reads out data from the switch buffer or the message memory based on the read out address and outputs the read out data to a time division frame. Synchronization instruction information is set individually for the individual data in the read control memory or the message memory, and only when an external synchronizing signal is present when data to be signaled for an individual channel us to be read out, the address read out by the read controller is used as an address for the message memory.

External signal synchronized message signaling apparatus for time division channel system

In an elastic store supplied with a sequence of reception data, a sequence of reception clock pulses, a sequence of reception frame pulses, a sequence of system clock pulses, and a sequence of system frame pulses comprising successive system frames each of which has a system frame phase, a first signal generating circuit alternately controls write-in operation of first and second data memory blocks in response to the reception clock pulses and the reception frame pulses. The first and the second data memory blocks thereby memorize the reception data as first and second memorized data, respectively. A second signal generating circuit alternately controls read-out operation of the first and the second data memory blocks in response to the system clock pulses and the system frame pulses. The first and the second data memory blocks thereby deliver the first and the second memorized data as first and second read-out data, respectively. A selector selects one of the first and the second read-out data as selected data and delivers the selected data as output data synchronized with the system frame phase within a predetermined phase difference.

Double buffer type elastic store comprising a pair of data memory blocks

An ISDN response system comprises a plurality of terminals, each of which contains a SETUP message to an incoming all. Each terminal has the same subscriber number with the same attribute values and responds to a first SETUP message received by it which has the aforementioned subscriber number and attribute values to transmit a CONN message to the termination so that communication is established between the network and the particular terminal, the CONN message of which is first received at the termination. The timing of the transmission of the CONN message sent by the particular terminal is delayed when a subsequent SETUP message is received having the same subscriber number and attribute values.

Response delay system of an ISDN terminal in a point to multipoint

The disclosed data switching apparatus comprises an input control unit which separates a header from communication data contained in logical channel data, as associative memory which compares the header with incoming logical channel numbers previously registered and which outputs an address control signal associated with an address where any of the incoming logical channel numbers coincident with the header are stored, a temporary storage circuit for outputting, based on the address control circuit, an outgoing logical channel number previously registered and associated with the coincident incoming logical channel number, a communication data buffer for temporarily storing the communication data, and an ouput control unit for combining the outgoing logical channel number from the temporary circuit and the communication data from the communication data buffer and delivering the combination to the outgoing communication channel.

Frame relay type data switching apparatus

A time switch with a dual structure-type control memory utilizing a time division time switch. The switch is equipped with a speech memory unit into which digital signals to be interchanged are temporarily written, and a control memory unit into which addresses to be accessed by the speech memory unit are written. The control memory unit has first and second memories. Each memory has an input/output section connected to a memory controller. The memories are set during hard and soft cycles so that when either one of the memories is set in a hard cycle the other memory is set in a soft cycle. The hard cycle is a speech-control data read-only mode. The soft cycle is a speech-control data read-write mode under control from the memory controller.

Time switch with a dual memory structure-type control memory

A packet switching system mainly consists of a packet transmission controller, connected to a line group, for performing transmission control of a data packet, and a packet switching unit for receiving the data packet from the packet transmission controller to perform switching processing. The packet switching unit includes a packet separator for separating the data packet into a header part and a data part, a packet header processor for updating the separated header part, a packet data buffer for storing the separated data part, and a packet combiner for combining the output from the packet data buffer and the output from the packet header processor and supplying a combined packet to the packet transmission controller.

Packet switching system

A subscriber line interface circuit described wherein a pair of line terminals are connected to a subscriber loop and a pair of output terminals are connected to a telecommunication exchange. A first amplifier is provided having a first pair of input terminals coupled to the line terminals and a second pair of input terminals. The first amplifier has a unity gain over a path from the input terminals of the first pair to said output terminals and a gain K over a path from the terminals of the second pair to said output terminals. A pair of reference resistors are cross-coupled from said output terminals to the line terminals, each of the reference resistors having a resistance Ro. A second amplifier is connected from the line terminals to the terminals of the second pair, the second amplifier having a transfer function -Ro/K.multidot.Zt, where Zt is an impedance to be synthesized across the line terminals.

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Tokyo, Japan

Hideyuki Hirata