Nec Corporation

Hideyuki Hasegawa

Kouichi Yamaguchi

Kazuhisa Sunaga

An equalization device () includes a sample hold unit () that samples and holds an input signal, a multiplication unit () that multiplies the output signal of the sample hold unit () by a coefficient, a sample hold unit () that samples and holds the input signal at a timing delayed from the sample hold timing of the sample hold unit () by one symbol length, a multiplication unit () that multiplies the output signal of the sample hold unit () by a coefficient, and an addition unit () that adds the output signal of the multiplication unit () and the output signal of the multiplication unit () to output a sum signal.

Equalization device, equalization method, and recording medium

Provided is an equalization device which receives a signal transmitted from a transmission side of the signal as an input signal, and equalizes the deterioration of a wave shape of the received input signal, wherein a bit value indicated by the input signal is judged in accordance with a clock on the basis of the wave shape of the input signal. From judged signals which result from the judgment and which are composed of a plurality of bits, a two-bit transition signal is detected so that the two-bit transition signal has two adjacent bit values having the same value, and bit values located before and after the two adjacent bit values are different from the bit value of the two adjacent bit values, and the phase of the clock is synchronized with the phase of the detected two-bit transition signal.

Equalization device, equalization method, and program

A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

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Tokyo, Japan

Hideyuki Hasegawa