Nec Corporation

Hideyuki Emura

Koichi Sato

Naotaka Maeda

Masamichi Kawarabayashi

Hitoshi Kurosaka

An apparatus for optimization of circuit design such as integrated circuits and printed circuits and an optimization process of the initial layout circuit, from results of the initial layout of the circuits, circuit connection informations after layout, cell positions, and interconnection routing, capacitance and resistance of interconnections are fetched. Optimization is made by local modification to the circuit such as cell placement and buffer insertion in consideration of keeping cell placements and interconnection routing so as to reduce delay, power consumption and circuit scale. Layout information to be changed by the local modification to the circuit is accurately recalculated on the basis of the original layout information. Renewed circuit connection information and newly calculated layout information are transmitted as restriction requirements to the layout section for conducting the relayout.

Apparatus for optimization of circuit design

In a register correspondence method in a logic equivalence verifying system for first and second sequential circuit information, input cone information is collected for each register of the first and second sequential circuit information. The input cone information is represented by external input terminals, determined registers, a number of undetermined registers and self-feedback information showing presence or absence of a self-feedback loop. Then, a first register having unique input cone information is selected from the first sequential circuit information, and a second register having unique input cone information is selected from the second sequential circuit information. Then, the input cone information of the first register is compared with that of the second register, thus establishing a register correspondence between the first and second registers.

Register correspondence method using I/O terminals, determined registers, the number of undetermined registers and self-feedback information to define unique registers

A delay optimization system including a layout processing unit for receiving the input of circuit specification of a target circuit to conduct layout, as well as extracting wiring information, an optimization processing unit for conducting optimization with reference to the wiring information, as well as generating circuit change information and inserted buffer information, and a constraints violations determining unit for determining whether a circuit generated as a result of the layout by the layout processing unit satisfies delay constraints set for the target circuit, the layout processing unit executing initial layout based only on circuit information synthesized based on the circuit specification of the target circuit and re-layout with reference to the circuit change information and inserted buffer information generated by the optimization processing unit.

Delay optimization system to conduct optimization for satisfying delay

A logic circuit verification device comprising a data input section to read the circuit data and the circuit information of the logic circuits to be verified and converts them into the intermediate format, a corresponding point detection section to extract and output the information about the corresponding points using the corresponding point detection algorithm, a circuit partitioning section to read the intermediate format data and partition the logic circuits according to the corresponding point information obtained by the corresponding point detection section so as to prepare circuit data of the subcircuits and a equivalence checking section to read the circuit data of the subcircuits, determine the subcircuits to be compared with referring to the corresponding point information obtained by the corresponding point detection section and comparatively compares the circuit data of the subcircuits.

Growing community of inventors

Tokyo, Japan

Hideyuki Emura