Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Hideyuki Arai

Takashi Nakabayashi

Takayuki Yamada

Tatsuya Kabe

Akio Misaka

Yasuko Tabata

Hisashi Aikawa

Masaru Sasago

Yoshihiro Sato

Mitsuyoshi Mori

Yusuke Sakata

Akito Inoue

Kentaro Nakanishi

Yuki Sugiura

Nobuyuki Matsuzawa

Mitsuo Nissa

Yasutoshi Okuno

Takashi Ohtsuka

Takehiro Hirai

Yuichi Higuchi

Tsutomu Oosuka

Yuji Nonami

Ryo Nakagawa

Yuya Sugasawa

Hiroji Shimizu

A light detector is configured such that a light receiving portion having APDs and a peripheral portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral portion has an n-type MISFET provided at a p-well and an n-well provided to surround entire side and bottom portions of the p-well.

Light detector

To provide a fused hetero 5-membered ring molecule having further sufficiently high hole mobility. Disclosed is a fused hetero 5-membered ring molecule having, in one molecule, eight aromatic rings including three or five hetero 5-membered rings, and the eight aromatic rings having one or two naphthalene structures. The three or five hetero 5-membered rings are each independently selected from the group consisting of a thiophene ring, a selenophene ring, and a furan ring.

Fused hetero 5-membered ring molecule, p-type semiconductor film and electronic device

To provide a fused thiophene molecule having further sufficiently high hole mobility. Disclosed is a fused thiophene molecule that has seven aromatic rings containing three thiophene rings in one molecule and in which the seven aromatic rings have one or two naphthalene structures. And, semiconductor devices including a layer using the fused thiophene molecule are disclosed.

Fused thiophene molecule and p-type semiconductor film and electronic device

A learning device includes a camera configured to acquire image data by imaging a sample of a product, a physical property information acquisition unit configured to acquire physical property information of the sample, and a processing unit configured to generate a learning model. The processing unit is configured to identify a category of the sample based on rule information relating the physical property information to the category, to generate teacher data by relating the identified category to the image data, and to generate a learning model by machine learning using the teacher data. The learning model outputs the category of the sample in response to an input of the image data of the sample.

Learning device, inspection device, learning method, and inspection method

A light detector is configured such that a light receiving portion having APDs and a peripheral circuit portion are provided on a first principal surface of a p-type semiconductor substrate, and further includes a back electrode provided on a second principal surface of the semiconductor substrate and a p-type first separation portion provided between the light receiving portion and the peripheral circuit portion. The APD has, on a first principal surface side, an n-type region and a p-epitaxial layer contacting the n-type region in a Z-direction. The peripheral circuit portion has an n-type MISFET provided at a p-well and an n-well provided to surround side and bottom portions of the p-well.

A semiconductor device includes a first laminated body and a second laminated body. The first laminated body includes sequentially a first element, a first wiring layer, and a first connection layer that includes a first junction electrode, on a main surface of a first substrate. The second laminated body includes sequentially a second element, a second wiring layer, and a second connection layer that includes a second junction electrode, on a main surface of a semiconductor substrate. The first laminated body and the second laminated body are bonded by directly bonding the first junction electrode and the second junction electrode with the two junction electrodes facing each other. A space region is formed at a part of a junction interface between the first laminated body and the second laminated body.

Semiconductor device and method for manufacturing same

A semiconductor devise includes a first substrate and a second substrate which are bonded each other. A first substrate includes an insulating first surface film as an uppermost layer, a first electrode and an insulating second surface film respectively formed inside a plurality of openings in the first surface film, and a first seal ring. A second substrate includes an insulating third surface film as an uppermost layer, and a second electrode, an insulating fourth surface film respectively formed inside a plurality of openings in the third surface film, and a second seal ring. The first electrode and the second electrode are directly bonded together. The first surface film and the third surface film are directly bonded together. The second surface film and the fourth surface film are directly bonded together. A seal ring formed of the first seal ring, the second surface film, the fourth surface film, and the second seal ring is continuous between the first substrate and the second substrate.

Semiconductor device and manufacturing method therefor

A semiconductor device includes first and second MIS transistors and a dummy element. The first MIS transistor includes a first gate insulating film which includes a first high-k insulating film formed on a first active region and contains an adjusting metal. The second MIS transistor includes a second gate insulating film which includes a second high-k insulating film formed on a second active region and is free of the adjusting metal. The dummy element includes a dummy gate insulating film which includes a dummy high-k insulating film formed on a dummy active region and at least a portion of which is free of the adjusting metal. The first active region is formed in a second conductivity type first well region. The second active region is formed in a first conductivity type second well region. The dummy active region is formed in a second conductivity type third well region.

Semiconductor device

A semiconductor device includes: a first substrate including a first surface layer that includes first and second electrodes; a second substrate including a second surface layer that includes third and fourth electrodes, and directly bonded to the first substrate such that the second surface layer is in contact with the first surface layer; and a functional film provided between the second and fourth electrodes. The first and third electrodes are bonded together so as to be in contact with each other, and the second electrode, the functional film, and the fourth electrode constitute a passive element.

Semiconductor device and method for fabricating the same

A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.

Semiconductor device and layout design method for the same

A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.

Semiconductor device having gate insulating film including high dielectric material

A semiconductor device includes a circuit portion including at least one real feature, and a plurality of dummy feature groups each including a plurality of dummy features spaced apart from each other by a first distance. The plurality of dummy feature groups are spaced apart from each other by a second distance larger than the first distance, and the circuit portion and the plurality of dummy feature groups are spaced apart from each other by the second distance.

Semiconductor device, mask for fabrication of semiconductor device, and optical proximity correction method

A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Growing community of inventors

Toyama, Japan

Hideyuki Arai