Kabushiki Kaisha Toshiba

Hideyoshi Takai

Takamichi Kasai

A semiconductor testing device includes: a data memory which stores a test program, said test program generating a test command for testing a plurality of functions within one function area of a plurality of function areas of a semiconductor device, said test command being generated for said function area; a first area generation part which generates first data, said first data identifying one function area of said plurality of function areas, said plurality of functions of said one function area being tested; a main control part which generates said test command based on said test program and said first data and transmits said test command to said semiconductor device; a second area generation part which receives a first result, said first result being returned from said semiconductor device based on a first test in accordance with said test command and generates a second result based on said first result, said second result showing a pass or failure of said first test corresponding to said function area; and a third area generation part which generates second data based on said second result and transmits said second data to said first area generation part, said first area generation part generating third data based on said second data, said third data identifying one or more of said plurality of function areas, said one or more of said plurality of function areas being the object of a second test subsequent to said first test.

Semiconductor testing device having test result sending back to generate second data

A semiconductor memory deviceis proposed including an internal address generation circuit, a first internal address control signal generation part, a second internal address control signal generation part, and an internal address control signal selection circuithaving an OR gate transistor. The internal address generation circuitgenerates an internal address signal based on input address data. The first internal address control signal generation partgenerates a first internal address control signal and having a function which fixes the first internal address control signal at a predetermined level with the elapse of a fixed period of time. The second internal address control signal generation partgenerates a second internal address control signal corresponding to an input of a predetermined command. The OR gate transistortransmits either the first internal address control signal or the second internal address control signal to the internal address generation circuit

Semiconductor memory device

A semiconductor integrated circuit device includes a semiconductor memory and a test circuit. The semiconductor memory includes a memory block having a plurality of memory cells and tests the memory cells. The test circuit includes a controller and a counter. The controller consecutively increments a gate voltage of the memory cells and controls the semiconductor memory so as to read a data from the memory cells provide with the gate voltage. The counter measures, for the gate voltage, the number of memory cells determined to be defective. The controller determines the memory block to be defective when the counter consecutively shows a count falling within a predetermined range during the variation in gate voltage.

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Tokyo, Japan

Hideyoshi Takai