Matsushita Electric Industrial Co., Ltd.

Hideya Esaki

Takehiro Hirai

Mitsuo Tanaka

Akihiro Kanda

Yoshiro Fujita

Toshio Yamada

Takashi Hirao

Yoshiro Nakata

Hakuhei Kawakami

Noriko Tsutsu

A sidewall insulating film is formed on the side faces of a gate electrode on a substrate. A trench isolation film is also formed to be self-aligned with the gate electrode. The upper surface of the trench isolation film reaches a level higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and the isolation film. Since the source/drain contacts and the isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region or the source/drain contacts (or source/drain regions) can be reduced in the gate length direction.

Semiconductor device having self-aligned structure

A sidewall insulating film is formed on the side faces of a buried gate electrode on a substrate. A trench isolation film, self-aligned with the gate electrode, is also formed so that the upper surface of the isolation film is higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and isolation film. Since the source/drain contacts and isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region and that of the source/drain contacts or source/drain regions can be reduced in the gate length direction.

Semiconductor device and method for fabricating the same

A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type; and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating extending films on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion layer of the first conduction type, a collector contact diffusion layer of the first conduction type, and a base contact diffusion layer of the second conduction type; locating an end of the emitter diffusion layer and a first end of the base contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the emitter lead-out electrode; and locating a second end of the base contact diffusion layer and an end of the collector contact diffusion layer at positions directly below a portion of the second insulating films which extends at a side of the collector lead-out electrode.

A method and apparatus for evaluating the lifetime of a semiconductor device are disclosed. Luminescence of a predetermined wavelength which is emitted from an operating semiconductor device is detected. The luminescence of the predetermined wavelength is one which correlates with the degradation of the semiconductor device. Then, the image of detected luminescence of the predetermined wavelength is processed to determine the place of the degradation caused by hot carriers.

Method of evaluating a semiconductor device and an apparatus for

A semiconductive memory in accordance with the present invention enables the correct setting of the reference electrical potential of a DRAM which is not affected by manufacturing processes by the use of a construction such that, into two dummy cell capacitors having the same capacitance as that of memory cell capacitors for holding information, signals of '1' and '0' or '0' and '1' are respectively written from the first and the second bit lines; thereafter, two dummy cell capacitors are electrically decoupled from the two bit lines and, then, by coupling two dummy cell capacitors, reference charges are obtained, which are then read out.

Semiconductor memory device having dummy cells of divided charge type

A MOS type semiconductor device, wherein at least one oblique face is provided on at least a part of a gate electrode which is provided on a principal face of said substrate with a gate insulation film inbetween, and at a specific depth from the oblique face, that is, in parallel with this oblique face, an ion-implanted layer is provided in a manner to obliquely cross the surface of said substrate. In this MOS type semiconductor device the channel is made immediately underneath the surface of the substrate and in the ion-implanted layer, and therefore the channel length is determined by the thickness of the ion-implanted layer. By controlling the thickness of the ion-implanted layer, a short channel length, which is required for improving the operating speed and/or the handling current capability of MOS type semiconductor devices, is obtainable.

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Osaka, Japan

Hideya Esaki