Hitachi, Ltd.

Hideya Akashi

Toru Shonai

Yuji Tsushima

Naoki Hamanaka

Keitaro Uehara

Toshio Okochi

Hiroaki Fujii

Masamori Kashiyama

Koichi Okazawa

Yoshiko Yasuda

Toshiaki Tarui

Yasuyuki Okada

Naonobu Sukegawa

Tetsuhiko Okada

Tadayuki Sakakibara

Masaru Koyanagi

Tshiaki Tarui

Tsuyoshi Tanaka

Naohiko Irie

Yoshiki Murakami

Tadaaki Isobe

Satoshi Muraoka

Isao Ohara

Disuke Yamane

Makoto Koga

Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.

Shared memory multiprocessor system

A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data from a cache data section in advance to a cache data controller, before reading a cache tag from a cache tag section and conducting cache hit check. If a cache hit has occurred, the cache data controller returns the data subjected to speculative reading as response data, at the time when the cache data controller has received a read request issued by the coherent controller.

Computer system utilizing speculative read requests to cache memory

Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit inter-connecting the node but directly to the unit designated by the unit information.

Shared memory multiprocessor performing cache coherence control and node controller therefor

A cache system comprising a cache tag bufferfor storing a part of a cache tag memory. When a memory processing request is issued from a processor, a cache control meansretrieves both of the cache tag memoryand the cache tag buffer. If a target cache block is present in the cache tag buffer, then, without waiting for a retrieval result of the cache tag memory, the cache control circuitaccesses the cache data memoryusing information of the cache block.

Cache system with a cache tag memory and a cache tag buffer

In a multiprocessor system of a main memory shared type having a plurality of nodes connected each other through signal lines; each of the plurality of nodes includes CPUs having caches therein, a main memory, and a node controller for performing communication control between the CPUs, main memory and ones of the nodes other than its own node. The node controller has a communication controller for controlling communication interface between the plurality of nodes, a crossbar for determining a processing sequence of memory access issued from at least one of the plurality of nodes to be directed to the main memories of the plurality of nodes, and crossbar controller for making valid or invalid the crossbar.

Node controller for performing cache coherence control and memory-shared multiprocessor system

Each node includes a node controller for decoding the control information and the address information for the access request issued by a processor or an I/O device, generating, based on the result of decoding, the cache coherence control information indicating whether the cache coherence control is required or not, the node information and the unit information for the transfer destination, and adding these information to the access request. An intra-node connection circuit for connecting the units in the node controller holds the cache coherence control information, the node information and the unit information added to the access request. When the cache coherence control information indicates that the cache coherence control is not required and the node information indicates the local node, then the intra-node connection circuit transfers the access request not to the inter-node connection circuit interconnecting the nodes but directly to the unit designated by the unit information.

A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.

Cache control method and cache controller

An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.

Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer

A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is &ldquo;0&rdquo;, a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

Shared memory multiprocessor performing cache coherency

In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

Multiprocessor system and methods for transmitting memory access transactions for the same

A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control circuits includes a summarized cache tag memory for storing &ldquo;summarized information&rdquo; which is information having a reduced number of bits by summarizing information on a cache tag portion in the cache memory and indicating whether each of blocks is effectively indexed in the cache tag portion. For cache coherence control, the summarized cache tag memory is first accessed, so that the cache tag portion is accessed only when it is determined that a target block is effectively indexed, to determine whether the cache coherence control for the node is required.

Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system

A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas

An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

Message passing distributed shared memory system that eliminates

A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is '0', a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

Growing community of inventors

Kunitachi, Japan

Hideya Akashi