Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Hiatchi, Ltd.

Hidetsugu Ogishi

Isamu Asano

Masakazu Sagawa

Mitsuaki Horiuchi

Jun Sugiura

Osamu Kasahara

Hideo Aoki

Tsuyoshi Tamaru

Yoshinao Kawasaki

Nobuo Owada

Osamu Tsuchiya

Toru Kaga

Fumio Ootsuka

Kazuyoshi Torii

Hiromichi Enami

Makoto Ogasawara

Keisuke Funatsu

Masatoshi Tsuneoka

Takayoshi Kogano

Sinichi Suzuki

Seiichirou Shirai

Atsushi Wakahara

Hiroyuki Akimori

Tunehiko Tubone

Ken Tsugane

Nobuhiro Otsuka

Yoshihiro Ikeda

Tomotsugu Shimmyo

Yoshitaka Tadaki

Atsushi Hiraiwa

Shinji Shimizu

Toshihiro Sekiguchi

Jun Murata

Hiroko Kaneko

Masami Ozawa

Masao Sakata

Shigeru Kobayashi

Katsuo Abe

Tsuneaki Kamei

Kazuhito Ichinose

Hideaki Shimamura

Ken Okutani

Takeshi Oyamada

A low resistance Co silicide layer with less leakage current is formed over the surface of the source and drain of a MISFET by optimizing the film forming conditions and annealing conditions upon formation of Co (cobalt) silicide. More specifically, a low resistance source and drain (ntype semiconductor regions, ptype semiconductor regions) with less junction leakage current are formed, upon formation of a Co silicide layer by heat treating a Co film deposited over the source and drain (ntype semiconductor regions, ptype semiconductor regions) of the MISFET, by depositing the Co film at a temperature as low as 200&#xb0; C. or less, carrying out heat treatment in three stages to convert the Co silicide layer from a dicobalt silicide (CoSi) layer to a cobalt monosilicide (CoSi) layer and, then, to a cobalt disilicide (CoSi) layer, successively.

Fabrication method of semiconductor integrated circuit device

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same

A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.

Semiconductor integrated circuit device having switching misfet and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM

A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided.

Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring therefor and method of producing such wiring

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

Semiconductor integrated circuit device, process for fabricating the

A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

Method of producing semiconductor integrated circuit device having

Method of forming teos oxide and silicon nitride passivation layer on

Semiconductor integrated circuit device having switching MISFET and

Semiconductor integrated circuit device process for fabricating the same

A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. An aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide QSi.sub.x, where Q is a refractory metal and x is between 0 and 2, is used as a protective layer, for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.

Growing community of inventors

Hachioji, Japan

Hidetsugu Ogishi