Other

Mitsubishi Denki Kabushiki Kaisha

Ryoden Semiconductor System Engineering Corporation

Hidetoshi Souno

Yasunori Yamashita

Atsushi Narazaki

Mitsuhiro Yano

Minoru Kawakami

The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an improvement for enhancing a gate breakdown voltage. In order to achieve the object, gate wirings (,), (,) and (,) are provided to keep away from an upper end (UE) of an edge of a gate trench (,) along its longitudinal direction. More specifically, the gate wiring (,) coupled integrally with an upper surface of a gate electrode (,) is formed apart from the upper end (UE) and the gate wiring (,) is formed on an insulating film (,) also apart from the upper end (UE). The two gate wirings (,) and (,) are connected to each other through the gate wiring (,) formed on a BPSG layer (,). Moreover, an upper face of the gate electrode (,) is positioned on the same level as an upper main surface of a semiconductor substrate (,) or therebelow in the vicinity of the upper end (UE). Consequently, a concentration of an electric field generated in insulating films (,) and (,) covering the upper end (UE) can be relieved or eliminated.

Insulated gate semiconductor device and method of manufacturing the same

An n.sup.+ semiconductor substrate (1) using a silicon wafer as a base material and including As includes oxygen of which the concentration is in the range of 12E17 atoms/cm.sup.3 to 20E17 atoms/cm.sup.3. The first epitaxial growth layer (2) of n type and a diffusion layer (3) of p type are formed in sequence on the second major surface (1S2) of the semiconductor substrate (1). The thickness of an epitaxial a growth layer (10) is set to be not more than 20 .mu.m. A trench (6) is formed so as to extend from a surface of the diffusion layer (3) to the inside of the first epitaxial growth layer (2). A gate oxide film (5) is formed on a bottom surface (6B) and a wall surface (6W) of the trench (6) and a conductive layer (11) fills the trench (6). An n-type source layer (4) is formed at a corner (6C) of the trench (6). After that, predetermined electrodes are formed and so on, to complete a device. With this structure, it is possible to reduce a leak current, prevent deterioration in main breakdown voltage and stabilize gate-oxide-film breakdown-voltage characteristics in a vertical MOSFET with trench gate.

Power semiconductor device and method for manufacturing the same

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Hyogo, Japan

Hidetoshi Souno