Fujitsu Corporation

Fujitsu Microcomputer Systems Limited

Fujitsu Microcomputer System Limited

Fujitsu Limited & Fujitsu Microcomputer Systems Ltd.

Hidetoshi Shimura

Shinji Oyamada

Takayoshi Taniai

Hiroyuki Fujiyama

Tadashi Saitoh

Kouichi Kuroiwa

Hajime Sato

Sinji Nishikawa

Shinji Nishikawa

Hajime Satoh

A data processing device contains art execution circuit and a data buffer circuit which stores one or more commands and/or one or more parameters which are prefetched, until each of the commands and parameters is read out by the execution circuit. The execution circuit inputs the oldest command stored in the data buffer circuit when an execution of a preceding command is completed, inputs one or more parameters stored in the data buffer circuit when the command input therein requests the parameters, and executes the command input therein, using the parameters when the parameters are input therein. The device further contains a circuit for detecting whether or not there is enough vacant space in the data buffer circuit in which a further command and/or a parameter can be stored, and another circuit for detecting a state of the data buffer circuit in which state the data buffer circuit does not store data including a command and/or a parameter, which is necessary for a next operation in the execution circuit. A prefetch control circuit, provided in either in the device or outside of the device, starts the prefetch operation and continues successive prefetch operations when the second state is detected, and stops the prefetch operation when the first state is detected. The system using the device contains a memory which stores the commands and parameters in the order of execution in the execution circuit.

System and device for prefetching command and parameters to be processed

A data control device which acquires the right to use a bus and performs data control includes a request circuit which selectively generates a plurality of request signals for acquiring the right to use corresponding buses. The plurality of request signals are based on attributes of data to be exchanged with an external device. The exchanged data includes data and commands.

Data control device generating different types of bus requests and

A grouping device comprises a register table and a grouping unit the register table having m registers corresponding to m groups, each register including an n-bits data storing portion corresponding to the n input signals, for registering relationships between the n input signals and the m groups, the grouping unit receiving grouping signals output from the register table and the n input signals, for selecting one group from the m groups for each input signal and grouping each input signal into the selected group in accordance with the register table. Therefore, the register access time is shortened and the confirmation of the contents of the register by the CPU is made easier.

Grouping device for forming input signals into groups

An interrupt processing method and an interrupt processing apparatus provides an end indicative information storing unit for storing an end indicative information of a daisy chain for at least one of a plurality peripheral units, the peripheral unit receiving the indicative information when the peripheral unit receives an acknowledge signal but does not output a request signal, and the peripheral unit outputs a specific chain end state signal to the central processing unit, so that the central processing unit is returned from a response waiting state. Therefore, when an error request signal is produced by noise, etc., delay at a central processing unit is reduced. Further, the daisy chain connection is cut at an optional portion and a request signal from an irrevelant peripheral unit is ignored, so that the efficiency of the processing is improved.

Method and apparatus for interrupt processing in a computer system

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Kawasaki, Japan

Hidetoshi Shimura