Canon Kabushiki Kaisha

Texas Instruments Corporation

Hidetoshi Onuma

Koichi Gunji

Yasuyuki Tanaka

Yasushi Ito

Manabu Umeyama

Hiroshi Miyaguchi

Tsuyoshi Akiyama

Kohichi Murohashi

Yugi Yaguchi

An image generation apparatus outputs image data to a display apparatus, performs inverse conversion on image data, and transmits the image data to the display apparatus through an external data transmission line. The display apparatus includes a display device that is capable of displaying a High Dynamic Range (HDR) image or a Standard Dynamic Range (SDR) image through the external data transmission line. The inverse conversion is performed with respect to light emission characteristics of the display device. The image data is generated by the light emission characteristic inverse conversion unit. The transmission is performed in a case where light emission characteristics of the display device approximate an Electro-Optical Transfer Function (EOTF) of the HDR, a bit precision of image data is no lower than a bit precision of the external data transmission line, and an image of the HDR is to be displayed on the display device.

Image display system for displaying high dynamic range image

An electronic apparatus provided with a display unit configured to display image data, comprises a synchronization control unit that generates a synchronization signal based on a display rate of the display unit, and an image processing unit that operates in accordance with an operating clock and execute image processing on image data to be displayed on the display unit at a display rate synchronized with the synchronization signal. The operating clock is not changed when the synchronization control unit changes a period of the synchronization signal in accordance with a change in a display rate of the display unit.

Electronic apparatus, method for controlling same, and computer readable medium

An image pickup apparatus includes a first image reduction unit configured to reduce the size of an image output by an image pickup element, a memory configured to store the image reduced by the first image reduction unit, an external output unit configured to output the image stored in the memory, a display configured to display an image being shot, a second image reduction unit configured to reduce, to the display size on the display, the image reduced by the first image reduction unit, without causing the reduced image to be stored in the memory and a signal processor for the display configured to perform signal processing of the image reduced to the display size on the display.

Image signal processing apparatus and a control method thereof, and an image pickup apparatus and a control method thereof

This invention controls the code generation quantity adaptively with respect to the pattern of images and changes in the images, etc., so as to alleviate degradation in image quality, and to effectively reduce the spatial redundancy in order to provide a margin in the code quantity and to improve the overall image quality. An adaptive filter has a coefficient table memory that holds N coefficient tables, filter coefficients F, F. . . Fthat provide different filtering characteristics, a filter coefficient selectingfor selecting one filter coefficient Ffrom filter coefficient tables and filter calculating unit performing prescribed calculations on the DCT coefficients using the selected filter coefficient F.

Image information compression device

The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP core of this SVP (Scan-line Video Processor) is made up of a three layer construction of the data input register (DIR) the SIMD type digital signal processing unit and the data output register (DOR) The SIMD type digital signal processing unit comprises a parallel arranged (connected) number of processing elements (PE to PEN&minus;1) (for example, 864 units) equal to the number of pixels N on one horizontal scan line. The instruction generator (IG) because the SVP core operates as an SIMD parallel processor, internally houses a RAM or ROM program memory that holds the desired program. The program stored in program memory contains not only the instructions (SIMD instruction) for the processing elements (PE to PEN&minus;1) of the processing unit but also such instructions (IG instruction) as jump, subroutine call, hardware interrupt, and the like. In this SVP when an IG instruction is read from the program memory while the repetitive processing of an SIMD instruction is being conducted in the SVP core the pertinent IG instruction is executed in parallel with the repetitive processing of the pertinent SIMD instruction.

Processor

A voltage controlled oscillator has a linear voltage to current characteristic from ground to the supply voltage. This oscillator includes a voltage to current converter which employs two output current paths. The first output current path includes an N-type MOSFET whose gate receives the input voltage. A level shifter circuit receives the input voltage and provides an output voltage shifted up by an amount equal to the input threshold voltage of an N-type MOSFET. A clamp circuit connected to the output of the level shifter circuit prevents this output voltage from becoming greater than a voltage equal to the sum of the input threshold voltage of an N-type MOSFET and the input threshold voltage of a P-type MOSFET. The gate of the second N-type MOSFET receives the output of the level shifter as clamped by the clamp circuit. A current mirror circuit supplies a current control to ring oscillator, whose frequency depends upon the current. A second embodiment includes a new ring oscillator. The voltage to current converter supplies two pair of N-type MOSFETs. The ring oscillator includes two phase control circuits, one for opposite phases of the oscillatory output.

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Tokyo, Japan

Hidetoshi Onuma