Kyoto University

Nippon Telegraph and Telephone Corporation

Japan Science and Technology Agency

Jedat Innovation Inc.

Hidetoshi Onodera

Hiroaki Katsurai

Yusuke Ohtomo

Akira Tsuchiya

Nobuto Ono

Islam A K M Mahfuzul

Xuliang Zhang

Islam AKM Mahfuzul

A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.

Reconfigurable delay circuit, delay monitor circuit using said delay circuit, variation compensation circuit, variation measurement method, and variation compensation method

An inductor () includes an inductor (LP) formed into the shape of a spiral on the outer circumference of an inductor region and having a start point connected to a terminal (NP), an inductor (LP) formed into the shape of a spiral on the inner circumference of the inductor region and having a start point at the end point of the inductor (LP) and an end point connected to a terminal (NP), and an inductor (LP) formed into the shape of a spiral in a region sandwiched between the inductor (LP) and the inductor (LP) and having a start point at a node between the inductor (LP) and the inductor (LP) and an end point connected to a terminal (NP).

Inductor

A CMOS model generating apparatusaccording to the present invention generates a CMOS model by converting an I-Ispace into an x-xspace such that a typical condition TT and corner conditions FF, SS in the I-Ispace become (0, 0), (&#x3b1;, &#x3b1;) and (&#x2212;&#x3b1;, &#x2212;&#x3b1;) in the x-xspace, determining an ellipse fitting to the respective mappings of the corner conditions FF, SS, FS and SF with the mapping (0, 0) of the typical condition TT as a center, expressing two independent principal components in the form of a Gaussian distribution using the major and minor axes of this ellipse as axes of the principal components, and obtaining a probability distribution determining deviations of the Gaussian distribution such that the cumulative probability within this ellipse becomes equal to the one presumed by the corner conditions FF, SS, FS and SF.

CMOS model generating apparatus and method, program of the method and recording medium

Growing community of inventors

Kyoto, Japan

Hidetoshi Onodera