Panasonic Corporation

Socionext Inc.

Matsushita Electric Industrial Co., Ltd.

Hidetoshi Nishimura

Masaki Tamaru

Kazuyuki Nakanishi

Tomoaki Ikegami

Hiroki Taniguchi

Hideaki Kondo

Ritsuko Ozoe

Junichi Yano

Nana Okamoto

Miwa Ichiryu

Emi Mizushino

Hiroyuki Uehara

Heiji Ikoma

Naoki Nojiri

Masahiro Gion

Tetsurou Toubou

Hiroyuki Shimbo

Hisako Yoneda

A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Semiconductor device

First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.

Semiconductor integrated circuit device

Semiconductor device comprising a plurality of cell arrays including a well potential supply region and adjacent dummy gates provided on a well region of a cell array

In a layout structure of a standard cell including off transistorsunnecessary for logic operation of a circuit, dummy via contactsare disposed on impurity diffusion regionsof the off transistors, respectively. Dummy metal interconnectsare connected to the dummy via contacts, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.

Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit

A first wiring () has a bending portion (), a first wiring region () extending from the bending portion () in the X direction, and a second wiring region () extending from the bending portion () in the Y direction. A via () is formed under the wiring (). The via () is formed so as not to overlap with a region of the bending portion () in the first wiring region (). The length of the via () in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via () in the Y direction overlap with both ends of the first wiring region () in the Y direction.

Semiconductor device including a first wiring having a bending portion a via

A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

Semiconductor integrated circuit device having improved interconnect accuracy near cell boundaries

A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.

Semiconductor integrated circuit

Semiconductor device including a first wiring having a bending portion and a via including the bending portion

There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

Semiconductor integrated circuit device having a dummy metal wiring line

Growing community of inventors

Osaka, Japan

Hidetoshi Nishimura