Denso Corporation

Nippondenso Co., Ltd.

Hidetoshi Muramoto

Mitsutaka Katada

Tadashi Hattori

Katsunori Abe

Yoshihiko Isobe

Seizi Fuzino

Akira Yamada

Seiji Fujino

Hiroyasu Itou

Masahiro Ogino

Hisayoshi Ooshima

Tomohisa Suzuki

A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply field trenches; and multiple field regions such that a k-th field region is surrounded with a k-th field trench. One MOS transistor is disposed in each field region. The MOS transistors are connected in series. The first MOS transistor has a gate terminal as an input terminal. The n-th MOS transistor is connected to the power source potential through an output resistor. The n-th field region has an electric potential, which is fixed to the power source potential.

Semiconductor device having first and second separation trenches

A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.

EEPROM and EEPROM manufacturing method

An MIS transistor fabricated in a manner that minimizes the occurrence of leak currents and that improves overall transistor performance by minimizing variation in location of the transistor source and drain during fabrication thereof. A gate electrode is first fabricated on a substrate. Next, a thermal oxide layer is formed on a side of the gate electrode. A masking process is then performed with the thermal oxide layer to form a source and a drain. A silicon oxide layer is then deposited over the gate electrode, the source and the drain. An etching process is performed on the silicon oxide to form a side wall oxide film over the thermal oxide layer on the side of the gate electrode and to expose surfaces of the gate electrode, the source and the drain. A metal film is then deposited over the gate electrode, the source and the drain and is heat treated to form a metal silicide film on the exposed surfaces of the gate electrode, the source and the drain. The side wall oxide film functions to disperse the metal silicide film as it is deposited to electrically separate the gate electrode, the source and the drain, thereby preventing a leakage current from occurring.

Insulated gate transistor with leakage current prevention feature

In a semiconductor device including high-voltage, middle-voltage, and low voltage transistors having operating voltages different from one another, a gate length and a thickness of a gate oxide film are increased as the operating voltage is increased. Accordingly, in the high-voltage transistor, an electric field produced at a channel is relaxed. In the low-voltage transistor, a structure is made finer. A concentration of a well and an impurity amount implanted into a surface portion of a substrate are set to be identical with each other in all the transistors. Accordingly, the semiconductor device can be speedily manufactured at a high yield.

Semiconductor device including several transistors and method of manufacturing the same

A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Method of fabricating a MIS transistor

Process for fabricating a complementary MIS transistor

A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

Growing community of inventors

Okazaki, Japan

Hidetoshi Muramoto