Fujitsu Corporation

Fujitsu Semiconductor Limited

Hidetoshi Matsuoka

Izumi Nitta

Toshiyuki Shibuya

Katsumi Homma

Hiroyuki Higuchi

Fumiyasu Hirose

Koichiro Takayama

Shintaro Shimogori

Hiroshi Ikeda

Kenji Nomura

Yoshinori Tomita

Hideshi Yamaguchi

Takuya Ohwa

Kioto Hirahara

A method includes: partitioning learning data containing objective variables and explanatory variables into a plurality of subsets of data; executing regularization processing on first data in each of the partitioned subsets, and extracting a first element equal to zero; extracting, as a candidate, each model where an error ratio between first multiple regression and second multiple regression is equal to or more than a predetermined value, the first multiple regression being a result of multiple regression on second data which is test data in each of the partitioned subsets and is for use to calculate the error ratio of the learning data, the second multiple regression being a result of multiple regression on third data obtained by excluding the first element from the second data; and outputting a model where zero is substituted for an element that takes zero a predetermined or larger number of times in the candidate.

Optimization apparatus, non-transitory computer-readable storage medium for storing optimization program, and optimization method

A method includes: for each of a delivery source and each of plural delivery destinations to which goods are delivered, receiving distance information indicating a distance between points, delivery amount information indicating a total delivery amount of the goods to each of the plural delivery destinations, and maximum delivery amount information indicating a maximum delivery amount per delivery; calculating a first cost to deliver the goods for the total delivery amount from the delivery source to each of the plural delivery destinations while setting the maximum delivery amount indicated by the maximum delivery amount information; calculating a second cost to deliver the goods for the total delivery amount from the delivery source to each of the delivery destinations; executing selection processing for selecting a delivery destination by using the first cost and the second cost; and creating a delivery plan by using a result of the selection processing.

Non-transitory computer-readable storage medium for storing delivery plan creation support program, delivery plan creation support method, and information processing apparatus

A semiconductor memory includes a memory cell array that includes data cells of x bits and redundant cells of y bits for each word; a position-data storage unit that stores, for each word, defective-cell position data of defective cells of the data cells and the redundant cells; and a read circuit that reads data from cells of x bits based on the defective-cell position data stored in the position-data storage unit for a specified word of which address is specified as read address, the cells of x bits being formed by the data cells of x bits and the redundant cells of y bits of the specified word other than the defective cells.

Semiconductor memory of which defective cell is replaceable with redundant cell and manufacturing method of semiconductor memory

Disclosed is a simulation method for simulating an operation of a device. The simulation method includes specifying, by a computer, a boundary between a non-defective status and a defective status of a product in design space with a design parameter as an origin. The boundary is specified according to a search using a search indicator defined based on an operating state different from an operating state of a determination indicator that determines the non-defective status and the defective status of the operation.

Indicator-based product design optimization to find defective and non-defective status

A design support apparatus includes a detecting unit, a determining unit, and an inserting unit. The detecting unit detects a via that connects wirings in a circuit to be designed that is expressed by layout information. The determining unit determines the connection position of a dummy via that does not connect wirings, to be on at least one of wirings connected to the via detected by the detecting unit. The inserting unit inserts the dummy via at the connection position determined by the determining unit.

Support method, design support apparatus, computer product using combination pattern is prepared in advance

A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtaining and the calculating plural times while changing the reference candidate value set.

Simulation parameter correction technique

A non-transitory computer-readable recording medium stores therein a model generating program that causes a computer capable of accessing a memory device storing, among coefficients and input variables making up a model formula expressing an object to be modeled, statistical values associated with the coefficients to execute: inputting a data group as a combination of an input value and an output value with respect to the object; determining, based on a joint probability joining a first probability of occurrence of the model formula as defined by the statistical values and the coefficients and a second probability of occurrence of the model formula as defined by the input variables and output variables, values of the coefficients to maximize the joint probability by giving the data group to the input variables and the output variables of the joint probability; and outputting the values of the coefficients determined in relation to the model formula.

Bayesian model generating computer product, apparatus, and method

A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.

Computer readable non-transitory medium storing design aiding program, design aiding apparatus, and design aiding method for determining performance index of an integrated circuit in worst case operation conditions

Design support method, design support apparatus, computer product

Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.

Circuit delay analyzer, circuit delay analyzing method, and computer product

An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.

Method and apparatus for repeat execution of delay analysis in circuit design

A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.

Circuit delay analyzing method, circuit delay analyzing apparatus, and computer product

A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.

Delay analysis device, delay analysis method, and computer product

A global routing method acquiring global routing between net terminals of cells placed on a VLSI chip. First, a Steiner tree is generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution. Then, partial correction of the Steiner tree is repeated so as not to increase a line length as far as possible in consideration of constraints such as a prohibiting region, a wiring capacity and layers based on the initial solution of the Steiner tree to obtain the global routing. The Steiner tree is corrected generating a path collection obtained by dividing the Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of 3 or more branches.

Method and apparatus for global routing, and storage medium having global routing program stored therein

All nodes in a network are classified into hierarchical groups. Each node belongs to any group in all hierarchical groups from the highest order group to the lowest order group. The node is assigned a hierarchical address corresponding to each hierarchical group. Thus, the amount of routing information required for data transfer can be reduced, thereby efficiently transmitting data.

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Kawasaki, Japan

Hidetoshi Matsuoka