Fujitsu Corporation

Hidetoshi Matsumura

Yasuhiro Watanabe

Akira Nakagawa

Hirotaka Tamura

Satoshi Shimada

Akihiro Yamori

Kouichi Kanda

An information processing device includes: a memory; and a processor coupled to the memory and configured to: convert target data into first data by predetermined arithmetic processing; generate second data based on the converted first data and identification information which specifies a file of the target data; and store the target data in an address of a memory corresponding to the generated second data.

Information processing device, information processing method, and data structure

An optimization device includes a plurality of calculation circuits; a selection circuit; an identification information calculation circuit, and an updating circuit. Each of the plurality of calculation circuits calculates, for a plurality of bits corresponding to a plurality of spins included in an Ising model obtained by converting a problem to be calculated, a first energy change of the Ising model due to a value of a first bit having the value of 1 being changed from 1 to 0 and a value of a second bit having the value of 0 being changed from 0 to 1. The selection circuit outputs first bit identification information identifying one second bit having a value permitted to be updated from 0 to 1, based on a magnitude relationship between thermal excitation energy and the first energy change output by each of the plurality of calculation circuits.

Optimization device and control method of optimization device

An information processing apparatus includes, a programmable circuit that includes multiple areas into which logics are capable of being programmed, a memory, and a processor configured to, receive a request including information concerning a first process and a second process, calculate a first throughput corresponding to the first process and a second throughput corresponding to the second process based on data used in each of the first process and the second process, determine a first number of areas in which the first process is performed and a second number of areas in which the second process is performed, and program first logics to perform the first process in first areas among the multiple areas, and program second logics to perform the second process in second areas among the multiple areas, the first areas corresponding to the first number, the second areas corresponding to the second number.

Information processing apparatus and information processing method

An information processing apparatus includes: a programmable circuit including a plurality of reconfigurable regions in which logic is reconfigurable; and a processor coupled to the programmable circuit, the processor being configured to (a): execute an extraction process that includes extracting, from the plurality of reconfigurable regions, one or more installable regions in which any of a plurality of first circuits is installable, (b): execute a first determination process that includes determining whether each of a plurality of second circuits is installable in a first reconfigurable region, (c): execute a second determination process that includes determining a first installation circuit and a first installation region based on the determination executed by the first determination process, and (d): execute an installation process that includes installing the first installation circuit determined by the second determination process in the first installation region determined by the second determination process.

Information processing apparatus, control method of information processing, and non-transitory computer-readable storage medium for storing program

A device is configured to control a programmable integrated circuit having a plurality of first areas each of which has the same shape and a plurality of second areas formed between the plurality of first areas. The device includes: a memory; and a processor configured to: recognize an operation request executed by the programmable integrated circuit, select a third area and a fourth area used for configuring an operational circuit, by which processing pertaining to the operation request, from the plurality of first areas and the plurality of second areas, cause the selected third area and the selected fourth area to function as an operation processing unit to generate the operational circuit, cause the generated operational circuit to execute processing pertaining to the operation request, and after the processing is completed, cause the third area included in the operational circuit to function as a communication path.

System including programmable integrated circuit including first areas having same shape and second areas formed between first areas, and operation processing device and method for controlling the programmable integrated circuit

A PLD control program causes a computer to execute process including: outputting a configuration request for configuring a logic circuit in any of a plurality of areas where logic circuits are enabled to be reconfigured in a programmable logic device (hereinafter referred to as a PLD); and selecting, when a total size or number of a plurality of first logic circuits already configured in the plurality of areas and a second logic circuit newly configured in accordance with the configuration request exceeds a size or a number of logic circuits that are enabled to be configured in the plurality of areas, a logic circuit to be replaced with the second logic circuit, as a replacement target, from among the plurality of first logic circuits, based on a save and restore time needed to save and restore state data in the first logic circuits.

Control program and control method for programmable logic device and information processing apparatus including the same

A quantization method includes: performing, by a computer, scaling on transform coefficients of a target block; quantizing scaled transform coefficients to obtain a plurality of quantization coefficients; calculating, when calculating, based on a quantization error and a first code amount of a coded target block obtained by coding the target block, a cost of coding the target block by using a coefficient absolute value candidate of a plurality of coefficient absolute value candidates of one of the plurality of quantization coefficients, the first code amount according to a second code amount of a coded element for the one of the plurality of quantization coefficients, the second code amount being obtained by binarizing the coded element under one of a first condition and a second condition.

Quantization method, coding apparatus, and computer-readable recording medium storing quantization program

A moving image processing apparatus cumulatively sums for each reference block and in a predetermined sequence, values representing differences between corresponding pixels in a first block of a reduced image of a given image and a reference block within a search range in a reduced reference image; detects a motion vector of the first block, based on a calculation result; compares the amounts of increase among intervals of the summing process when the evaluation value is calculated for the reference block represented by the motion vector; and based on the comparison, determines a sequence to be used when the evaluation value of the reference block is calculated by cumulatively summing the values that represent differences between corresponding pixels in a second block in the given image and corresponding to the first block, and in a reference block within a search range in the reference image indicated by the motion vector.

Moving image processing apparatus, moving image processing method, and computer product

The apparatus includes: orthogonal transforming means for orthogonally transforming an input video signal for each element block, quantizing means for quantizing each obtained transformation coefficient using a quantization parameter; coding means for coding the quantization parameter; decoded picture generating means for generating a reference picture signal for a motion compensation prediction from the quantized results of the quantizing means; filtering means for filtering the obtained reference picture signal at a strength corresponding to the quantization parameter when a non-zero effective transformation coefficient is present with respect to the element block; and controlling means for controlling at least anyone of transformation coefficients to be not zero, when all of the transformation coefficients are zero. This allows, even when all of the quantized results of the transformation coefficients of the element blocks are zero, coding of quantization parameter of current element block and control of filtering strength.

Apparatus and method for coding moving pictures

A decoding section for decoding inputted first data; a first memory for being adapted to store second data obtained by decoding the first data; a second memory for being adapted to store error information on an error in decoding of the first data; and an output section for outputting the second data, wherein when the output section reads and outputs the second data from the first memory, the output section reads and outputs, as data corresponding to an error of the first data, second data stored in the second memory and serving as a decoding result of the other part of the first data based on the error information stored in the second memory.

Semiconductor device and method of controlling the same

A moving picture decoding apparatus includes one or more variable-length decoding units, a data buffer configured to store data output from the one or more variable-length decoding units, and a plurality of image decoding units configured to read the data from the data buffer and to perform image decoding the data.

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Kawasaki, Japan

Hidetoshi Matsumura