Taiyo Yuden Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Hidetoshi Masuda

Kotaro Mizuno

Yoshinari Take

Masaru Kurosawa

Kenichi Ota

Yoichi Kato

Yukio Tamai

Taisei Irieda

Toshimasa Suzuki

Hidechika Kawazoe

Naoto Hagiwara

Kazuki Yamada

Nobuyoshi Awaya

Shinji Kobayashi

Minoru Ryu

Riki Suemasa

Kazushi Yawata

Atsushi Shimaoka

Kenji Kawano

Yuji Matsushita

Yuji Nishi

Koichi Tsukagoshi

Teruo Atsumi

Yoshio Aoyagi

A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. There are a concentration peak of a first metal and a concentration peak of a second metal at different positions in a stacking direction of the plurality of internal electrode layers and the plurality of dielectric layers between a dielectric layer and an internal electrode layer next to the dielectric layer, the first metal and the second metal being different from a main component metal of the plurality of internal electrode layers. The second metal is easier to ionize than the first metal. The concentration peak of the second metal is closer to the dielectric layer than the concentration peak of the first metal.

Ceramic electronic device with multilayer chip having concentration peaks of metal elements between internal electrode layers and dielectric layers, and manufacturing method of same

A ceramic electronic device includes a multilayer chip in which dielectric layers and internal electrode layers are alternately stacked. The internal electrode layers include a main component element and a sub-element. The dielectric layers include a plurality of crystal grains. A segregation portion, in which the sub-element is segregated in shell portions and a grain boundary of the plurality of crystal grains and a sub-element concentration is 1.5 times or more as that in an entire of each of the dielectric layers, is formed. near an interface between each of the internal electrode layers and each of the dielectric layers, each of the internal electrode layers has a high concentration layer, in which the sub-element concentration is 1.5 times or more as that in an entire of each of the internal electrode layers.

Ceramic electronic device and manufacturing method of the same

A capacitor that can make a failure mode into an open mode even when a short circuit caused by insulation breakdown occurs in a dielectric layer is provided. The capacitor includes: a substrate; an MIM structure disposed on the Substrate, the MIM structure including a dielectric layer, a bottom electrode layer disposed on one side of the dielectric layer and composed of a first conductive material, and a top electrode layer disposed on the other side of the dielectric layer; a first external electrode disposed on the substrate; a second external electrode disposed on the substrate; and a connection conductor connecting between the bottom electrode layer and the first external electrode, the connection conductor including a first contact portion contacting the substrate.

Capacitor with connection conductor contacting a surface of a substrate

A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of a plurality of internal electrode layers are alternately stacked. The plurality of internal electrode layers include Ni and Sn. Each of an upper section and a lower section of the plurality of internal electrode layers includes multiple internal electrode layers each having a Sn concentration higher than that of each internal electrode layer of a center section interposed between the upper and lower sections in a stacking direction, which are constituted by top 5% or more and bottom 5% or more of the plurality of internal electrode layers, respectively.

A ceramic electronic device includes a multilayer body in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. In at least a part of a cover layer and side margins, a concentration of a specific metal of at least one of Ag, As, Au, Bi, Co, Cr, Cu, Fe, Ge, In, Ir, Mo, Os, Pd, Pt, Re, Rh, Ru, Se, Sn, Te, W or Zn is lower on an outer side than on a side of the multilayer body.

Ceramic electronic device

A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers of which a main component is ceramic and each of three or more of internal electrode layers are alternately stacked. The three or more of internal electrode layers include Ni and Sn. An internal electrode layer having a larger Sn concentration is closer to an outermost edge in a stacking direction than an internal electrode layer having a smaller Sn concentration and being located on a center side of the stacking direction, in a relationship of at least two of the three or more of internal electrode layers.

A manufacturing method of a multilayer ceramic electronic device includes: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure, whereby each internal electrode layer is formed from the each of internal electrode patterns and each dielectric layer is formed from the each of the dielectric green sheets wherein, in the each internal electrode layer, an Au concentration near each interface between the each internal electrode layer and the each dielectric layer is larger than an Au concentration in each center portion in a thickness direction.

Manufacturing method of multilayer ceramic electronic device

A ceramic electronic device includes a multilayer chip in which a dielectric layer and an internal electrode layer are alternately stacked. Concentration peaks of two or more types of metals different from a main component metal of the internal electrode layer exist at different positions in a stacking direction of the dielectric layer and the internal electrode layer, between the dielectric layer and the internal electrode layer.

A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Au. Each of the plurality of internal electrode layers includes an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between the each of the plurality of internal electrode layers and a dielectric layer next to the each of the plurality of internal electrode layers. A relationship of C&#x2264;500&#xd7;t/T is satisfied when a thickness of the each of the plurality of internal electrode layers is T nm, a thickness of the Au-containing layer is t nm, and an Au concentration with respect to a total of Ni and Au in a whole of the each of the plurality of internal electrode layers is C at %.

A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.

A trench capacitor according to one embodiment of the present invention includes a base member with an upper surface having a plurality of trenches provided therein and an MIM structure provided on the base member so as to be embedded in the plurality of trenches. In the embodiment, the plurality of trenches include a first trench and a second trench adjacent to the first trench in a first direction orthogonal to a depth direction of the plurality of trenches. The base member includes a first wall separating the first trench from the second trench. The first wall includes a first portion having an acute angle at a distal end thereof in a section including the first direction and the depth direction.

Trench capacitor

A capacitor includes a dielectric layer, a first conductive layer, a second conductive layer, first inner electrodes, second inner electrodes, a first external power electrode layer, a second external power electrode layer, a first outer electrode, and a second outer electrode. The first and second inner electrodes and first and second second outer electrodes are a conductive material. The dielectric layer has through-holes connecting with a first main surface and a second main surface. The first inner electrodes are in a first set of the through-holes and connected to the first conductive layer. The second inner electrodes are in a second set of the through-holes and connected to the second conductive layer. The first outer electrode is on the first external power electrode layer and some side-faces of the dielectric layer. The second outer electrode is on the second external power electrode layer and some side-faces of the dielectric layer.

Capacitor

A capacitor includes a dielectric layer having a first plane, a second plane opposite to the first plane, and a plurality of through-holes communicated with the first and second planes; a first external electrode layer disposed on the first plane; a second external electrode layer disposed on the second plane; a first internal electrode having first and second electrode portions, the first and second electrode portions being formed of a first conductive material, and a second conductive material, respectively, the second electrode material connecting the first electrode portion with the first external electrode layer, the second conductive material having a smaller Young's modulus than the first conductive material, the first internal electrode being formed in a part of the plurality of through-holes; and a second internal electrode formed in another part of the plurality of through-holes, the second internal electrode being connected to the second external electrode layer.

A capacitor includes a dielectric layer having a first plane, a second plane opposite to the first plane, and first and second through-holes communicated with the first plane and the second plane; a first external conductor layer disposed on the first plane; a second external conductor layer disposed on the second plane; a first internal electrode formed in the first through-hole, connected to the first external electrode layer, disposed in the second hole diameter part at a tip and separated from the second external electrode layer; and a second internal electrode formed in the second through-hole, connected to the second external electrode layer, and separated from the first external electrode layer.

A capacitor includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode portion, a second internal electrode portion, and a close contact portion. The dielectric layer includes a first surface, a second surface facing the first surface, and a plurality of through-holes communicating between the first surface and the second surface. The first internal electrode portion is provided on a first through-hole portion. The second internal electrode portion is provided on a second through-hole portion. The close contact portion brings at least one of the first external electrode layer and the second external electrode layer into close contact with the dielectric layer, the close contact portion being provided on a third through-hole portion, the third through-hole portion being the remaining portion of the plurality of through-holes.

Growing community of inventors

Tokyo, Japan

Hidetoshi Masuda