Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Texas Instruments Corporation

Elpida Memory, Inc.

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Hokkai Semiconductor Ltd.

Hidetoshi Iwai

Masamichi Ishihara

Kazuyuki Miyazawa

Yasushi Takahashi

Masaya Muranaka

Yutaka Ito

Kousuke Okuyama

Tetsuro Matsumoto

Hisao Katto

Hiromi Matsuura

Kazumichi Mitsusada

Shigetoshi Sakomura

Hiroyuki Uchiyama

Ryoichi Hori

Hisashi Nakamura

Toshitsugu Takekuma

Toshiyuki Sakuta

Kazuya Ito

Takumi Nasu

Yoshihisa Koyama

Shunichi Sukegawa

Masayuki M Nakamura

Toshio Suzuki

Satoshi Oguchi

Hidetomo Aoyagi

Haruo Ii

Wataru Arakawa

Takeshi Kizaki

Yoshinobu Nakagome

Masanori Tazunoki

Toshitugu Takekuma

Kiyoshi Inoue

Masakazu Aoki

Katsutaka Kimura

Hirotaka Nishizawa

Toshio Sasaki

Kazuyoshi Oshima

Katsuhiro Shimohigashi

Hiromasa Noda

Toshio Sugano

Toshio Yamada

Yoshitaka Tadaki

Katsuyuki Sato

Osamu Tsuchiya

Kiyoshi Nakai

Toshihiro Sekiguchi

Yasunori Yamaguchi

Jun Murata

Yasuhiro Kasama

Youji Idei

Eiji Miyamoto

Katsuo Komatsuzaki

Masahiro Yamamura

Seiichiro Tsukui

Jiro Sawada

Makoto Saeki

Tadao Kaji

Masayasu Kawamura

Yoshitaka Kinoshita

Toshio Maeda

Tomohiro Suzuki

Takashi Araki

Osamu Sakai

Shinobu Takeura

Noboru Shiozawa

Norihiko Kasai

Ichirou Anjou

Eiji Yamasaki

Satoru Koshiba

Yutaka Itou

Masakatsu Goto

Yoshiaki Anata

Yasushi Sekine

Tetsuji Kohara

Sadao Morita

Tomoyoshi Miura

Mutsuo Tsukuda

Toshitugu Takemuma

Tomoshi Matsumoto, Deceased

Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

Semiconductor memory device

When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Data storing method of dynamic RAM and semiconductor memory device

A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

Semiconductor integrated circuit device

In a semiconductor memory device which is intended to have a smaller sense amplifier forming area to match with small-sized bit lines, first bit lines BL (e.g., BL ) are formed on a first layer, and lines M (e.g., M ) are formed on a second layer and connected to the first bit lines in a first connecting area located between a first memory cell area and a sense amplifier area. Second bit lines BL (e.g., BL ) are formed on the first layer, and lines M (e.g., M ) are formed on the second layer and connected to the second bit lines in a second connecting area located between a second memory cell area and the sense amplifier area. As a result, the lines M on the second layer can have a smaller line interval.

Memory semiconductor device with reduced sense amplifier area

A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with an identical pitch, and, also, alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed to have the vertical construction and the bit line located at the upper side of the substrate, where a channel region is formed, is shielded with a conductive film, a part of which forms the gate electrode.

Semiconductor device

A semiconductor integrated circuit device includes in a P-type well region containing a memory substrate a array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage. Accordingly, the P-type well region provided with the input circuit or the output circuit corresponding to the external terminals is fed with the back bias voltage to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit can be raised.

Semiconductor integrated circuit device, and process and apparatus for

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (103) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

Method of making mask pattern data and process for manufacturing the mask

To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.

Semiconductor memory device and defective memory cell correction circuit

A semiconductor integrated circuit device includes in a substrate a P-type well region containing a memory array section in which dynamic memory cells are arranged in a matrix. The P-type well region is fed with a back bias voltage whose absolute value is reduced so as to be the most suitable for the refresh characteristics. Also included is a P-well region wherein there are formed N-channel MOSFETs of a peripheral circuit this P-well region is fed with a back bias voltage whose absolute value is smaller than that of the potential fed to the P-type well of the memory array section, considering the high-speed operation. A P-type well section, wherein there is formed are N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is fed with a back bias voltage whose absolute value is made large considering an undershoot voltage. The P-type well region provided with the memory array section is fed with a requisite minimum back bias voltage. Accordingly, the P-type well region provided with the input circuit or the output circuit corresponding to the external terminals is fed with the back bias voltage to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit can be raised.

A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

Dynamic memory device, a memory module, and a method of refreshing a

Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

Method of fabrication of semiconductor integrated circuit device

Growing community of inventors

Ohme, Japan

Hidetoshi Iwai