Toshiba Memory Corporation

Kioxia Corporation

Kabushiki Kaisha Toshiba

Hideto Takekida

Reiko Shamoto

Tatsuo Izumi

Takahisa Kanemura

Shigeo Kondo

Kaito Shirai

Hideo Wada

Fumitaka Arai

Satoshi Nagashima

Wataru Sakamoto

Hisataka Meguro

Kazuhiro Nojima

Takaya Yamanaka

Kenta Yamada

Keisuke Suda

Hisakazu Matsumori

Naoyuki Iida

Akira Mino

Kohei Nyui

Mikiko Yagi

Masaharu Mizutani

Jun Murakami

Kazuma Takahashi

Ryo Hikida

Shotaro Kuzukawa

A semiconductor storage device includes: a first semiconductor layer through first conductive layers; a gate insulating film between the first conductive layers and the first semiconductor layer; a first structure facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layer and the first structure; a third semiconductor layer between the second semiconductor layer and the first conductive layers; a fourth semiconductor layer including a first portion along a bottom surface of the third semiconductor layer and a second portion along a top surface of the second semiconductor layer; and a first insulating layer, between the first and second portions, including a first region spaced from the first structure with a distance longer than a first distance that contains a nitride film, and a second region spaced from the first structure with a distance shorter than the first distance that does not contain nitrogen.

Semiconductor storage device and manufacturing method thereof

According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.

Semiconductor memory device

A semiconductor device includes a substrate, a first external connection pad separated from the substrate in a first direction, which is a thickness direction thereof, a first coil separated from the substrate in the first direction and electrically connected to the connection pad, a first stacked body between the connection pad and the substrate and between the first coil and the substrate, the first stacked body including a first insulator, a first wiring therein, and a first pad electrically connected to the wiring, and a second stacked body between the first stacked body and the substrate, the second stacked body including a second insulator, a second wiring therein, a second pad electrically connected to the second wiring, and a second coil. The first insulator contacts the second insulator. The first pad contacts the second pad. A part of the first coil overlaps the second coil in the first direction.

Semiconductor device

According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.

Memory device

A semiconductor storage device includes a stack, a channel layer, a first charge storage portion, and a second charge storage portion. The stack includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The channel layer extends in the first direction in the stack. The first charge storage portion is provided between the channel layer and each of the plurality of conductive layers in a second direction intersecting with the first direction. The second charge storage portion includes a portion interposed between two adjacent conductive layers in the plurality of conductive layers in the first direction.

Semiconductor storage device and method of manufacturing semiconductor storage device

A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.

Semiconductor storage device with insulating layers for etching stop

A semiconductor storage device includes a substrate, a first stacked body provided above the substrate and having a side portion configured in a staircase pattern, a plurality of columnar portions passing through the first stacked body, a second stacked body provided in an outer edge portion of the substrate, and a plurality of first slits. The first stacked body include a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked. The second stacked body includes the plurality of first insulating layers and the plurality of conductive layers that are alternately stacked. The plurality of first slits extends through the first and second stacked bodies in a direction intersecting a stacking direction of the first stacked body.

Semiconductor storage device

A semiconductor device is provided, including: a substrate; a first stacked portion including a plurality of first electrode layers stacked in a first direction via a first insulator; a second stacked portion provided above the first stacked portion and including a plurality of second electrode layers stacked in the first direction via a second insulator; a connection portion provided between the first stacked portion and the second stacked portion, and including a third insulator; a column-shaped portion extending in the first stacked portion, the second stacked portion, and the connection portion in the first direction, and including a semiconductor body and a charge storage portion; and a semiconductor pillar provided between the substrate and the column-shaped portion, and in contact with the substrate and the semiconductor body of the column-shaped portion.

Semiconductor device and method of manufacturing the same

According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.

A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.

According to an embodiment, a semiconductor memory device includes first and second memory cells and a controller. In a program operation, the controller applies a first voltage to a select gate line at a first timing, applies a second voltage to a select gate line at a second timing, applies a third voltage to a word line at a third timing, and applies a fifth voltage to a word line at a fifth timing. In a program operation when the first memory cell is selected, a time between the second timing and the third timing is a first time. In a program operation when the second memory cell is selected, a time between the second timing and the third timing is a second time different from the first time.

Systems and methods to control semiconductor memory device in various timings

According to an embodiment, a memory device comprises a conductive layer containing a metal, a semiconductor layer on the conductive layer, electrode layers stacked on the semiconductor layer in a stacking direction, a semiconductor pillar penetrating the electrode layers in the stacking direction and electrically connected to the semiconductor layer, and a charge trap layer between the electrode layers and the semiconductor pillar. The conductive layer has a recess or a through-hole below the semiconductor pillar.

Three-dimensional NAND memory device with source line comprising metallic and semiconductor layers

According to one embodiment, a semiconductor memory includes a plurality of conductors stacked with insulators being interposed therebetween and a pillar through the plurality of conductors. The pillar includes a first columnar section, a second columnar section, and a joint portion between the first columnar section and the second columnar section. The pillar comprises portions that cross the respective conductors and that each function as part of a transistor. The plurality of conductors include a first conductor. The first conductor is closest to the joint portion among the plurality of conductors through the second columnar section, and includes a bending portion formed along the joint portion.

Three dimensional semiconductor memory including pillars having joint portions between columnar sections

A memory device includes a plurality of word lines spaced from one another in a first direction, a first insulating film provided between adjacent word lines, a plurality of select gates located above the plurality of word lines in the first direction, a first intermediate electrode provided between the plurality of word lines and the select gates, a second insulating film provided between the first intermediate electrode and the select gates, a semiconductor pillar extending through the plurality of word lines, the first insulating film, the first intermediate electrode, the second insulating film, and the select gates, and extending in the first direction, and a charge retention film located between each of the plurality of word lines and the semiconductor pillar, wherein the second insulating film has a second thickness in the first direction that is greater than a first thickness of the first insulating film in the first direction.

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Nagoya, Japan

Hideto Takekida