International Business Machines Corporation

Hideto Niijima

Takashi Toyooka

Akashi Satoh

Yoshinori Sakaue

Nobuaki Takahashi

Seiji Munetoh

Hiroki Murata

Mayumi Shimada

Nobuyuki Matsuo

Hideo Asano

Yoshinao Kobayashi

Apparatus method for calculating the remainder of B.sup.C modulo n at high speed with minimum hardware resources, while securing the safety of the key in a cryptographic system. The apparatus comprises circuitry including registers for executing an initial and normal cycles, cumulating and storing the calculation result of each cycle and for outputting from a least significant bit. The initial cycle of the calculation includes a step of calculating a remainder of an m-bit input modulo n and a step of holding the result of the calculation. The normal cycle of the calculation includes a step of doubling the result of the calculation, and calculating a remainder of the doubled result of the calculation modulo n and a step of holding the next result of the calculation and for repeatedly executing the normal cycle m-2 times after the first normal cycle. The calculation result of each previous normal cycle is used in each successive normal cycle.

Apparatus and method for calculating B.sup.c (mod n)

A data storage system is provided having a faster data transfer rate and reduced complexity though improved control of timing. The data storage system has a plurality of storage devices and a plurality of data buses through which data are transferred. An input/output unit interleaves a plurality of data between an interface and the plurality of data buses while transferring data. A first and a second latch unit, serially connected between the storage devices and the data bus, retain data.

Data storage system, data transfer method, and data reconstruction method

The present invention provides a method and apparatus for generating parity in a data storage system. The data storage system includes two or more storage devices having data stored therein, two or more data buses through which the data is transferred, and a selector located between the storage devices and the buses which selectively connects the storage devices and the data buses by a predetermined combination. The selector further includes the capability of calculating parity operations such as an XOR operation. The selector performs the parity operations to logically combine data transferred through the selector between the data buses and the storage devices to produce parity data on the combined data transferred so as to reduce the data transfers over the data bus.

Data storage system and parity generation method for data storage system

A system is provided for improving the speed for writing data in a disk array system. The disk array system includes a solid state disk storage device configured with semiconductor flash memory to sequentially store the parity for the disk array. The solid state disk storage device allows data sectors to be assigned sequentially in a cluster consisting of a set of blocks. Each block is a physical unit of erasure. Write operations for a plurality of sectors are written across the set of blocks in the cluster.

Disk array system and method for storing data

A disk storage device includes two data buses 100, 200 for data transfer. Hard disks (HDDs) 0 and 1 are permanently connected to the data buses 100, 200, and hard disks 2 and 3 are selectively connectable to either of the data buses. When a microcontroller (MCU) 32 outputs a specified signal to a data path controller (DPC) 10 in response to a command from a host, multiplexers 20, 22 connect the selectively connectable hard disks 2 and 3 to one of the data buses. When data is written to or read from the hard disks, the write or read can be performed quickly with fewer data buses and a simple device configuration. A parity data generator (PGEN) 24 is connected to both of the buses, receiving new data via one bus and writing new parity data via the other bus.

Disk storage device

An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

Flash-erase-type nonvolatile semiconductor storage device

A method and system are provided for improving the speed for writing data in a disk array system (RAID). Disks are divided into the ones for reading old data and the other ones for writing new data. An external semiconductor storage device is used as a parity device which significantly enhances performance in writing. A disk array system is used for storing data for which a parity group comprises N data units stored in sectors of N magnetic disk drives with parity stored in the parity device. At least N+1 data-storing magnetic disk drives are provided, where sectors of at least one magnetic disk drive are used as redundant sectors.

With the present invention, the page table of the program code non-continuously placed in an external storage device using randomly accessible and rewritable memory is built into an executable sequence in a virtual address space of the CPU according to the execution order. By referring to the address translation tables, including the page table, the system is able to read the program from the external storage device, thereby executing the program. Therefore, the program can be executed without being loaded into main memory. Furthermore, the program and data can be managed without distinction. Further, with the randomly accessible memory according to the present invention, since a sequence of real addresses of the CPU are assigned to the data area, control over the direct execution of the program can be simply achieved. Furthermore, since data and ECC parity can also be read and written sequentially, the system has good compatibility with a hard disk system. Since the data and Ecc parity are present on the same word line and can be accessed without changing the page address, simple control is achieved.

Control method and apparatus for direct execution of a program on an

An object of the present invention is to provide a data storage system and a parity generation method for the data storage system which make generation of parity easier and which are capable of performing the reconstruction of data at the time of an occurrence of failure with high efficiency and high speed. A data storage system is provided comprising a plurality of devices for storing data, a plurality of data buses for transferring the data, and a selector connected between the plurality of devices and the plurality of data buses for selectively connecting a device and a data bus using a predetermined combination, the selector including a parity operation generator.

A nonvolatile memory with flash erase capability includes a plurality of clusters each having a plurality of sectors, each of the sectors holding the attribute information for identification. A cluster information sector is placed at the top of a cluster to which it belongs. A data sector is placed in a data area which is the region other than the top of the cluster. A controller connected to the nonvolatile memory creates a cluster information copy sector when erasing a cluster, and reconstructs cluster management information from the cluster information copy sector when initializing a cluster, thereby forming a cluster information sector. Accordingly, endurance against failure such as power failure in a solid state file apparatus using the nonvolatile memory is improved.

Nonvolatile memory with flash erase capability

A method and system are provided for improving the speed for writing data in a disk array system (RAID). Sectors of the disks are divided into the ones for reading old data and the other ones for writing new data. An external semiconductor storage device is used as a parity device which significantly enhances performance in writing. Preferably, a disk array system is used for storing data for which a parity group comprises N data units stored in sectors of N magnetic disk drives with parity stored in the parity device. At least N+1 magnetic disk drives are provided, where sectors of at least one magnetic disk drive are used as redundant sectors.

A nonvolatile memory-with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.

Nonvolatile memory with cluster-erase flash capability and solid state

To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effectively used over a long period of time. An address control scheme was introduced in which flexibility is given to the address relation between the host CPU and the external storage and the physical address of the semiconductor memory is not one-sidedly determined by the logical address possessed by the command of the host CPU. Command processing section 34 always prepares memory blocks and sectors for writing or erasing and copying in preparation for the command processing of the host CPU, and records and holds the correspondence relation between the physical address of the selected memory block 32i or sector and the command of the host CPU in address conversion table 36. The status of memory blocks and sectors is recorded in respective managing tables 35 and 60, and used for control of processings such as writing, erasing and copying in preparation for or in response to the command of the host CPU.

External information storage system with a semiconductor memory

An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the validity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

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Tokyo, Japan

Hideto Niijima