Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Hideto Horii

Tomoya Sanuki

Hiroki Tokuhira

Hideaki Aochi

Takashi Maeda

Yasuhito Yoshimizu

Keisuke Nakatsuka

Masaki Kondo

Naoyuki Shigyo

Yusuke Higashi

Hiroki Kawai

Shuichi Toriyama

Tomoya Kawai

Kunihiro Yamada

Kazuya Matsuzawa

Takao Kosaka

Tatsuo Ogura

Michiru Hogyoku

A semiconductor device includes a first conductive layer extending along a first direction, a semiconductor layer extending along a second direction crossing the first direction, penetrating the first conductive layer, and including an oxide semiconductor, a first insulating layer between the first conductive layer and the semiconductor layer, a second conductive layer provided on one side of the semiconductor layer in the second direction and electrically connected thereto, a third conductive layer provided on the other side of the semiconductor layer in the second direction and electrically connected thereto, an electric conductor extending from the third conductive layer toward the second conductive layer along the semiconductor layer, and a charge storage film between the semiconductor layer and the electric conductor.

Semiconductor device and semiconductor storage device

A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

Memory system

An example semiconductor device includes: n conductive layers including first to nconductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nconductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to ncharge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.

System and method for controlling semiconductor memory device including multiple charge storage regions

A semiconductor memory device includes a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, respectively, and a row control circuit. The row control circuit is configured to apply a program voltage to a first word line among the word lines while stepping up a value of the program voltage; apply a first pass voltage to a second word line among the word lines different from the first word line when applying the program voltage having a voltage value equal to or greater than a predetermined voltage value to the first word line; and apply a second pass voltage having a voltage value higher than the first pass voltage to the second word line when applying the program voltage having a voltage value less than the predetermined voltage value to the first word line.

Semiconductor memory device and data writing method

In a write operation to memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is not less than a reference value,

Semiconductor memory device and method of manufacturing the same

A non-volatile semiconductor memory device according to one aspect of an embodiment of the present invention includes: a semiconductor substrate; an element region; a plurality of memory cell transistors which each include a control gate electrode; and programming means for programming data to a programming target memory cell transistor by applying a programming voltage to the programming target memory cell transistor. Moreover, the programming means applies a programming voltage incremented stepwise from an initial programming voltage, to the programming target memory cell transistor while applying a constant initial intermediate voltage to memory cell transistors adjacent to the programming target memory cell transistor. Thereafter, the programming means applies an intermediate voltage incremented stepwise from the initial intermediate voltage, to one of the respective memory cells adjacent to the programming target memory cell transistor, while applying a constant final programming voltage to the programming target memory cell transistor.

Non-volatile semiconductor memory device and a programming method thereof

According to one embodiment, a NAND nonvolatile semiconductor memory device comprises memory cell transistors and a write circuit. The memory cell transistors are arranged in a matrix in a column direction and in a row direction. Each of the memory cell transistors comprises a charge accumulation layer and a control gate electrode configured to control the charge accumulation state of the charge accumulation layer. The write circuit carries out write on the memory cell transistors. The memory cell transistors arranged in the same line include first memory cell transistors and second memory cell transistors that are smaller than the first memory cell transistors in the column direction. The write circuit carries out write on a predetermined first memory cell transistor and then on another first memory cell transistor. After the write on the another first memory cell transistor, the write circuit carries out write on the second memory cell transistor.

NAND nonvolatile semiconductor memory device and write method for NAND nonvolatile semiconductor memory device

Growing community of inventors

Yokohama, Japan

Hideto Horii