Hitachi, Ltd.

Renesas Technology Corp.

Hidetaka Shigi

Susumu Kasukabe

Terutaka Mori

Takayoshi Watanabe

Akihiko Ariga

Haruhiko Matsuyama

Makoto Kitano

Ryuji Kohno

Yasuhiro Motoyama

Kunio Matsumoto

Tetsuo Kumazawa

Naoto Ban

Yuji Wada

Ryuji Kono

Shuji Shibuya

Takashi Inoue

Hideo Sotokawa

Tetsuya Yamazaki

Hitoshi Yokono

Naoki Matsushima

Eiji Matsuzaki

Fusaji Shoji

Koji Suzuki

Yasunori Narizuka

Masashi Nishiki

Mamoru Ogihara

Hideo Todokoro

Jun Tanaka

Katsuhiro Kuroda

Satoru Fukuhara

Norio Saitou

Kaoru Katayama

Fumio Kataoka

Hideo Arima

Akira Yabushita

Masakazu Yamamoto

Takaji Takenaka

Yukio Maeda

Takehiko Hasebe

Genya Matsuoka

Naoya Kitamura

Tositada Netsu

Minoru Tanaka

Masayuki Kyooi

Mitsuo Yoshimoto

Shirou Akamatsu

Shogi Ikeda

Miharu Otani

Toshio Terouchi

To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.

Connection device and test system

A semiconductor device capable of facilitating high density mounting at low cost without causing any defective conduction at the time of connection to a substrate, a mounting structure thereof and a method of fabrication thereof, characterized in that pyramidal bump electrodes are bonded onto pad electrodes arranged on a semiconductor chip to form the semiconductor device.

Method for producing a semiconductor device with pyramidal bump electrodes bonded onto pad electrodes arranged on a semiconductor chip

Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step

A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows. Subsequently, second windows of a particular shape are provided in regions of layers of the insulating resin filled in the windows, and independent conducting paths are formed through the second windows to extend from front sides of the second windows to back sides thereof. The conducting paths are formed radially to be spaced a substantially equal distance from centers of the respective second windows.

Multi-layer wiring substrate and manufacturing method thereof

A connection device and test system is capable of stable, low load damage-free probing of devices under test, which have many pins with a narrow pitch. Furthermore in order to achieve high speed exchange of electrical signals or so-called high frequency electrical signals, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film, a contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member, and a compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.

Connector and probing system

Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.

A multilayer wiring system for preventing the generation of fixing failure due to an organic residue, eliminating an increase in the number of processes and reducing an area necessary for bonding of the cap and its fabrication method. The multilayer wiring board includes at least one wiring layer made of a conductor, at least one insulating layer made of an organic matter and a board. The wiring layer and the insulating layer are alternately laminated on the board and a cap is provided for covering the insulating layer and the wiring layer. The wiring layer has a wiring pattern for forming a wiring and a frame pattern for surrounding the wiring pattern. This frame pattern includes vent holes. The insulating layer has a shield structure made of an inorganic matter around the outer peripheral portion thereof and/or in the interior thereof. The shield structure is formed of the frame patterns continuously connected to each other and the cap is joined to an uppermost layer of the shield structure.

Multilayer wiring board having vent holes and method of making

Circuit board and method of manufacturing the same

A metalization structure having a first conductor layer on the surface of an underlying layer and, further, a second conductor layer connected conductively with the first conductor layer in which a polyimide insulative film of low thermal expansion coefficient is present between at least an end of a pattern of the second conductor layer and the first conductor layer, for stably obtaining a metalization structure of high reliability and free from the worry of peeling of the conductor portion from a substrate or occurrence of cracking to the underlying layer.

Metalization structure and manufacturing method thereof

The present invention provides the wiring structure having a wiring layer and insulation layer and the method of manufacturing the same, wherein at least a part of the wiring of said wiring layer comprises copper, and said insulation layer comprises the polyimide obtained by heating the polyimide precursor composition containing the polyimide precursor having the repeating unit which can be represented by the following general formula (Chemical formula 15). ##STR1## (In this formula, R.sup.1 is at least one type of quadrivalent organic group selected from among the Chemical formulae 16, while R.sup.2 is a bivalent organic group containing aromatic ring).

Wiring structures and method of manufacturing the same

A circuit board is manufactured by a method having the steps of depositing a metal pattern on a ceramic board, depositing a thin layer of a high polymer material on the ceramic board formed with the metal pattern, depositing a protective layer of a high polymer material on the thin layer of the high polymer material, and directing a laser beam toward and onto the protective layer and the thin layer deposited on a plating region of the metal pattern and a cutting region of the ceramic board thereby selectively removing part of those layers. The laser beam has a wavelength range of from 150 nm to 400 nm, an energy density range of from 0.5 J/cm.sup.2 to 5.0 J/cm.sup.2, and a pulse width range of from 100 ps to 1 .mu.s.

Circuit board and sealing structure and methods for manufacturing the

Growing community of inventors

Hakone-machi, Japan

Hidetaka Shigi