Sony Computer Entertainment Inc.

Lsi Logic Corporation

Sony Computer Entertainment America LLC

Lsi Corporation

Sony Corporation Entertainment Inc.

Sony Interactive Entertainment Inc.

Hidetaka Magoshi

Nobuo Sasaki

Aaron G Wells

Ho-Ming Leung

Robert L Caulk, Jr

Kevin L Daberkow

An apparatus including a processor and a memory. The processor may be configured to process pixel data comprising eight or more bits. For pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of the pixel are packed with LSBs from one or more other pixels into a second byte. The memory may be coupled to the processor and configured to store the first byte in response to a first pointer and the second byte in response to a second pointer. The first byte and the second byte are stored independently in the memory.

Hybrid multiple bit-depth video processing architecture

Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include a plurality of memory lines, the number of memory lines corresponding to the number of cache lines in a way set of the first level cache memory. Alternatively, the memory lines may include L-flags for multiple cache lines of each way set of the next lower level cache memory. L-flags associated with a given index plus any index offset from the first level cache memory may be contained in a single memory line of the additional memory.

Methods and apparatus for controlling hierarchical cache memory

Methods and apparatus permit: reading a rewritable storage medium, the rewritable storage medium including digital content and a flag indicative of whether the digital content is encrypted; determining whether the digital content of the rewritable storage medium is encrypted based on the flag; encrypting the digital content of the rewritable storage medium using an identification (ID) number as an encryption key when the flag indicates that the digital content is not encrypted, the ID number being unique to a processing apparatus operable to execute the digital content; and overwriting the digital content of the rewritable storage medium with the encrypted digital content.

Methods and apparatus for customizing a rewritable storage medium

A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the jump instruction if it was.

System and method for processing complex computer instructions

Methods and apparatus for producing an electronic ID number include modifying at least one physical bit element from among each of at least first and second groups of physical bit elements, each physical bit element of each group having a first physical state in which it is operable to produce a signal having a first electrical state, and being capable of permanent modification to a second physical state in which it is operable to produce a signal having a second electrical state; and producing (i) one bit of an identification (ID) number from the respective signals issuing from each of the respective at least first and second groups of physical bit elements, and (ii) a validity signal indicative of whether the one bit of the ID number is valid.

Methods and apparatus for composing an identification number

A multi-processing computer architecture and a method of operating the same are provided. The multi-processing architecture provides a main processor and multiple sub-processors cascaded together to efficiently execute loop operations. The main processor executes operations outside of a loop and controls the loop. The multiple sub-processors are operably interconnected, and are each assigned by the main processor to a given loop iteration. Each sub-processor is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor.

Methods and apparatus for multi-processing execution of computer instructions

A system and method for handling complex instructions includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the Jump instruction if it was.

Methods and apparatus for controlling hierarchical cache memories permit: controlling a first level cache memory including a plurality of cache lines, each cache line being operable to store an address tag and data; controlling a next lower level cache memory including a plurality of cache lines, each cache line being operable to store an address tag, status flags, and data, the status flags of each cache line including an L-flag; and setting the L-flag of a given cache line of the next lower level cache memory to indicate whether or not a corresponding one the of the cache lines of the first level cache memory has been refilled with a copy of the data stored in the given cache line of the next lower level cache memory.

A method is provided for use in a processing pipeline operable to dispatch a plurality of instructions up to a first number of instructions per cycle to execution stages of the pipeline. According to such method, a skip instruction is decoded in a first cycle of the processing pipeline to determine a total number of subsequent instructions in the processing pipeline that are to be skipped. The skip instruction is executed in a second cycle. Subsequent instructions in the processing pipeline are prohibited from being executed, including prohibiting execution of a second number of instructions subsequent to the skip instruction in the second cycle, the second number being variable between zero and one less than the first number. Thereafter, if any subsequent instructions of the total number remain to be skipped, then a third number of instructions are prohibited from being executed in a third cycle subsequent to the second cycle, the third number being variable up to the lesser of: the number of subsequent instructions which remain to be skipped and the first number.

Counting instructions to skip in superscaler processor

Character (or letter) information is extracted from source information, word information is extracted from the character information, and a database is created of the word information. Thereby, the created database is adapted for the technical field of the user or a field of interest to the user.

Method for creating a database such as a dictionary used for a word conversion system

Methods and apparatus enable: the partitioning of a main memory into a plurality of blocks, each block being adjacent to at least one of the other blocks, and each block including a plurality of data units containing one or more bits of data; the partitioning of each block of the main memory into a plurality of zones, each zone containing one or more of the data units; the association of at least some of the respective zones of each given block with respective others of the adjacent blocks to the given block; and the pre-fetching of a given one of the other blocks into a cache memory when any one of the data units within any of the associated zones of that block is addressed.

Methods and apparatus for controlling a cache memory

Methods and apparatus for controlling a cache memory are described in which the overwriting of floating point data into any cache line of the cache memory is prohibited when the data stored in such cache line are valid, integer data.

A semiconductor device includes a transmission line bounded by a first buffer and a second buffer. The first and second buffers are placed such that the transmission line has a length between a minimum and a maximum, thereby permitting narrow clock signal pulses to be transmitted with reduced distortion.

Growing community of inventors

Palo Alto, CA, United States of America

Hidetaka Magoshi