Oki Electric Industry Co., Ltd.

Hidetaka Kodama

Yasuhiro Shin

Tatsuya Kimura

Hiroshi Furuya

Kenji Kokuda

A driving circuit for an active-matrix liquid-crystal display short-circuits at least two of the signal lines in the matrix at times of transitions of signal-line potentials in the matrix. Charge stored in the parasitic capacitances of the signal lines is thereby recycled from one signal line to another, reducing the current consumption of the driving circuit. When alternating-current driving is employed, current consumption can also be reduced by reducing the frequency with which signal lines are driven from one side of a center potential to the other side.

Liquid-crystal display driving circuit and method

An integrated circuit comprising a circuit block whose power supply is controlled by waiting operation, is supplied which is able to prevent the occurrence of penetrating electricity caused by unstable signals output from the circuit block whose power supply was broken. In the integrated circuit, a mask signal is set at 'L' level before a power in the circuit block is broken, a latch circuit formed by a NAND and an inverter keeps a node in 'L' state, then when the power supply is broken and drops into &#x201c;L&#x201d; level, the output signal of the NAND is fixed in &#x201c;H&#x201d; level. Thus, from the circuit block, even if a unstable mask signal is output, the node keeps in &#x201c;L&#x201d; level, so that gate circuits become off.

Integrated circuit

In a semiconductor integrated circuit having an LVT (low threshold voltage) block and an HVT (high threshold voltage) block, a power switch controls power supply to the LVT block. An output wrapper fixes a level of an output signal from the LVT block to a predetermined level when no power is supplied to the LVT block, and an input wrapper fixes a level of an input voltage inputted into the LVT block to a predetermined level when no power is supplied to the LVT block. As a result, low current consumption can be realized and malfunctions can be prevented in a power-down mode.

Semiconductor integrated circuit

An oscillation circuit for outputting an oscillation signal includes a comparison circuit and a reference signal generation circuit. The comparison circuit compares two voltage levels and outputs a comparison result as the oscillation signal. The reference signal generation circuit provides a signal input to the comparison circuit. The reference signal generation circuit includes at least two resistance means coupled with each other in series, where one resistance means is given a smaller regulation of the resistance value relative to the temperature as compared with other resistance means.

Oscillation circuit using comparator with temperature compensated reference voltages

Semiconductor memory device and method for reading data therefrom

A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the second decode line group and the second input terminal for selecting the second decode lines in response to the second signal.

Word line selection circuit for selecting memory cells

Word line selection circuit for simultaneously selecting a plurality of

A drive device with a data latch circuit which is formed of a plurality of latches, which successively latch serial drive data and output them in parallel, and a shift register having a plurality of first flip-flops which provide, responsive to clock pulses, latch signals for causing the latch to latch the serial data in succession. In one aspect of the invention, the shift register also outputs an end signal when output of the latch signals is completed, and a gate circuit which blocks input of the serial data to the data latch circuit responsive to the end signal. In another aspect of the invention, the shift register has a second flip-flop which produces an output signal after output of the latch signals to said plurality of latches is completed, and a logic gate circuit receiving a latch complete signal that is output from one of the first flip-flops upon completion of the output of the latch signals, and the output signal from the second flip-flop, and outputs a signal of the predetermined level for a predetermined period. A blocking circuit blocks the serial data or the clock pulse responsive to an end signal output from the second flip-flop.

Growing community of inventors

Tokyo, Japan

Hidetaka Kodama