Fujitsu Corporation

Hidetaka Kawahara

Hiromichi Makishima

Hiroyuki Kitajima

Wataru Odashima

Shingo Hotta

Masayuki Tanaka

Junichi Sugiyama

Akihiko Oka

Keiichiro Tsukamoto

Hiroyuki Homma

Yuji Obana

Shota Shinohara

Kazumasa Mikami

Masanori Hiramoto

An Add Drop Multiplexer (ADM) includes a separating unit that extracts, from an ODU4 storing therein a plurality of HO-ODUs each of which stores therein at least one LO-ODU, first MSI values which correspond to the HO-ODUs and each of which identifies a different one of the LO-ODUs for each LO-ODU. The ADM includes a converting unit that converts the first MSI values which correspond to the HO-ODUs and each of which identifies a different one of the LO-ODUs, into second MSI values which correspond to the ODU4 and each of which identifies a different one of the LO-ODUs. The ADM includes an ODU processing unit that extracts the LO-ODUs from the ODU4, on the basis of the second MSI values resulting from the conversion by the converting unit.

Transfer apparatus and transfer method

A transmission apparatus includes: a generator configured to generate position information indicating a position of header information of each of a plurality of first signals from a second signal nesting the plurality of first signals; a storage configured to store the position information generated by the generator and the plurality of first signals; a monitor configured to read the position information and the plurality of first signals stored in the storage, and to monitor the header information of each of the plurality of first signals based on the position information; and an output unit configured to output the plurality of first signals after monitoring the contents of the header information.

Transmission apparatus and transmission method

A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.

Transmission device

A data transmission device where a low-speed signal transmission frame is included in time slots of a high-speed signal transmission frame and a number of the time slots to include the low-speed signal transmission frame is variable, wherein the time slots have respective time slot numbers, includes a storage unit storing signal data of the high-speed signal transmission frame corresponding to the number of the time slots based on a time slot number basis, wherein the signal data of the high-speed signal transmission frame are supplied on the time slot number basis; and a selection and output unit selecting and sequentially outputting the signal data on the time slot number basis, wherein the signal data have been stored in accordance with the number of the time slots.

Data transmission apparatus and data transmission method

A disclosed precoder circuit is used for differential phase shift keying and includes multiple levels of parallel precoder units, each of which is configured to perform a precoding operation using a data signal having multiple symbols and one of a fixed value and a one-symbol preceding modulated signal output from a preceding-level parallel precoder unit so as to obtain a modulated signal, precoding operations of the parallel precoder units being simultaneously performed in a parallel fashion; multiple levels of re-timing units configured to synchronize modulated signals output from the parallel precoder units; and multiple levels of offset units, each of which is configured to add a phase difference between the fixed value and the one-symbol preceding modulated signal to the modulated signals output from the corresponding re-timing units.

Precoder circuit

A signal loopback device including a multiplexing/demultiplexing unit to carry out multiplexing/demultiplexing between a DS3 signal serving as a digital signal conforming to a DS3 C-bit parity system and a DS1 signal, a DS1 signal loopback storage unit to return the DS1 signal, a DS3 signal loopback storage unit to return the DS3 signal in an original input signal format, a selecting unit to select any one of DS3 loopback signals from the multiplexing/demultiplexing unit and the DS3 signal loopback storage unit, a protected detecting unit to output, when detecting loopback execution/cancellation information a plurality of times, a result of detection showing that loopback is to be executed or canceled, and a loopback control unit to make a control for loopback execution or loopback cancellation to the DS1 signal loopback storage unit, the DS3 signal loopback storage unit, and the selecting unit depending upon the result of detection.

Growing community of inventors

Shimotsuga, Japan

Hidetaka Kawahara