Fujitsu Corporation

Fujitsu Semiconductor Limited

Renesas Electronics Corporation

Fujitsu Ten Limited

Renesas Technology Corp.

Fujitsu Microelectronics Limited

Hidetaka Ebeshu

Yukio Ishikawa

Yasuyuki Umezaki

Kaoru Noumi

Susumu Nishihashi

Shigeo Koide

Yukio Fujisawa

Hiroaki Shimauchi

Tomoyuki Katou

Hideaki Tomatsuri

Hirotoshi Okada

Kouji Arai

A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.

Gateway apparatus and data transfer control method

An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Error detector and error detection method

A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.

Gateway apparatus and data managing method

Upon reception of data via a first communication device, a unit connects the first communication device with a storage unit to store the data to be transferred and, after completion of data reception, the unit switches connections of the storage unit to a second communication device and transmits the stored data to the second communication device.

Data transferring device for transferring data sent from one communication device to another communication device

The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.

Cache system with limited number of tag memory accesses

A CPU performs read access to a plurality of resources. A plurality of buffers connect the plurality of resources to the CPU, respectively. The CPU causes one of the plurality of buffers connected to one of the plurality of resources to be in an active state so that the CPU can perform read access to the one of the plurality of resources via the one of the plurality of buffers, the one of the plurality of resources being given priority.

Semiconductor apparatus and read access method

A microprocessor that includes a processor (6) for executing an instruction in accordance with an internal clock signal, an instructing section (3) for outputting a frequency multiplication rate instructing signal corresponding to the data output from the processor, and a data selecting section (2) for selectively outputting the frequency multiplication rate instructing signal. A PLL section changes the frequency of the internal clock signal in response to the frequency multiplication rate instructing signal output from the data selecting section. Inhibiting section inhibits the internal clock signal from being supplied from a PLL section to the processor for a predetermined period until the frequency of the internal clock signal in the PLL section becomes stable.

Growing community of inventors

Kawasaki, Japan

Hidetaka Ebeshu